公开(公告)号：US10970217B1

公开(公告)日：2021-04-06

申请号：US16422647

申请日：2019-05-24

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  Millind Mittal

IPC: G06F12/06 ,  G06F12/08 ,  G06F12/02 ,  G06F9/50 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/4401 ,  G06F13/40

Abstract: Embodiments disclosed herein provide a domain aware data migration scheme between processing elements, memory, and various caches in a CC-NUMA system. The scheme creates domain awareness in data migration operations, such as Direct Cache Transfer (DCT) operation, stashing operation, and in the allocation of policies of snoop filters and private, shared, or inline caches. The scheme defines a hardware-software interface to communicate locality information (also referred herein as affinity information or proximity information) and subsequent hardware behavior for optimal data migration, thus overcoming traditional CC-NUMA limitations.

公开(公告)号：US10922226B1

公开(公告)日：2021-02-16

申请号：US16208260

申请日：2018-12-03

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Chetan Loke

IPC: G06F12/00 ,  G06F12/0804 ,  G06F12/10 ,  G06F12/0891 ,  G06F12/0888

Abstract: An example computing system includes a memory, a peripheral device configured to send a page request for accessing the memory, the page request indicating whether the page request is for regular memory or scratchpad memory, and a processor having a memory management unit (MMU). The MMU is configured to receive the page request and prevent memory pages from being marked dirty in response to the page request indicating scratchpad memory.

公开(公告)号：US20200341941A1

公开(公告)日：2020-10-29

申请号：US16396540

申请日：2019-04-26

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Millind Mittal

IPC: G06F15/78 ,  H04L12/66 ,  G06N20/00 ,  G06F13/42 ,  G06F9/54

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators previously only used an I/O domain. In the embodiments herein, compute resources can be split between the I/O domain and the coherent domain where a ML engine is in the I/O domain and a ML model is in the coherent domain. An advantage of doing so is that the ML model can be coherently updated using a reference ML model stored in the host.

公开(公告)号：US10698824B1

公开(公告)日：2020-06-30

申请号：US16141704

申请日：2018-09-25

Applicant: Xilinx, Inc.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F3/00 ,  G06F12/0815

Abstract: Disclosed systems and methods include in each agent, an agent layer, a link layer, and a port layer. The agent layer looks-up a port identifier in an address-to-port identifier map in response to a request directed to another agent and submits the request to the port layer. The link layer includes a plurality of links, and each link buffers communications from and to the agent layer. The port layer looks-up, in response to the request from the agent layer, a link identifier and chip identifier and writes the request to one of the links identified by the link identifier and associated with the chip identifier. The port layer also reads requests from the links and submits communications to a transport layer circuit based on the requests read from the links and associated chip identifiers.

公开(公告)号：US20200044895A1

公开(公告)日：2020-02-06

申请号：US16053384

申请日：2018-08-02

Applicant: Xilinx, Inc.

Inventor： Millind Mittal ,  Kiran S. Puranik ,  Jaideep Dastidar

IPC: H04L12/54 ,  H04L29/06

Abstract: A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.

公开(公告)号：US12235950B2

公开(公告)日：2025-02-25

申请号：US17578292

申请日：2022-01-18

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  James Murray ,  Stefano Stabellini

IPC: G06F21/53 ,  G06F9/455

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

公开(公告)号：US11995021B2

公开(公告)日：2024-05-28

申请号：US17574342

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  David James Riddoch ,  Steven Leslie Pope

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4265 ,  G06F13/1684

Abstract: Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.

公开(公告)号：US11983133B2

公开(公告)日：2024-05-14

申请号：US17892949

申请日：2022-08-22

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  David James Riddoch ,  Steven Leslie Pope

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4027 ,  G06F13/28

Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).

公开(公告)号：US11983117B2

公开(公告)日：2024-05-14

申请号：US17826074

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F12/0891 ,  G06F3/06 ,  G06F9/50 ,  G06F12/0815

CPC classification number: G06F12/0891 ,  G06F3/0607 ,  G06F3/0652 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0815

Abstract: The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.

公开(公告)号：US11947459B2

公开(公告)日：2024-04-02

申请号：US17449561

申请日：2021-09-30

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  James Murray

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.