公开(公告)号：US12223355B2

公开(公告)日：2025-02-11

申请号：US17455074

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F9/44 ,  G06F9/50

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

公开(公告)号：US12047275B2

公开(公告)日：2024-07-23

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Jaideep Dastidar ,  Jeffrey Cuppett ,  Sagheer Ahmad

IPC: H04L45/24 ,  H04L45/74 ,  H04L49/109

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US11683038B1

公开(公告)日：2023-06-20

申请号：US17350639

申请日：2021-06-17

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/17712

Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.

公开(公告)号：US20230153156A1

公开(公告)日：2023-05-18

申请号：US17455074

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

公开(公告)号：US11563639B1

公开(公告)日：2023-01-24

申请号：US16025762

申请日：2018-07-02

Applicant: Xilinx, Inc.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: H04L41/12 ,  H04L41/0803

Abstract: In an example, a system specifies a first configuration of the physical transport network that models a plurality of devices as a corresponding first plurality of nodes having a tree topology. Each node of the first plurality of nodes has at least one first device identifier and at least one first connection identifier to other nodes in the tree topology. The system specifies a second configuration of the logical transport network that models the plurality of devices as the first plurality of nodes having a non-tree topology. Each node of the first plurality of nodes has at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology. The system folds the logical transport network over the physical transport network using the at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology.

公开(公告)号：US11474871B1

公开(公告)日：2022-10-18

申请号：US16582958

申请日：2019-09-25

Applicant: XILINX, INC.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F9/50 ,  G06F12/0815 ,  G06F9/455 ,  G06F9/38

Abstract: The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and a third layer containing accelerator function threads (AFTs) in each of the AFEs. Partitioning the hardware circuitry using multiple layers in the virtualization framework allows the accelerator to be quickly re-provisioned in response to requests made by guest operation systems or virtual machines executing in a host. Further, using the layers to partition the hardware permits the host to re-provision sub-portions of the accelerator while the remaining portions of the accelerator continue to operate as normal.

公开(公告)号：US11375050B1

公开(公告)日：2022-06-28

申请号：US17019039

申请日：2020-09-11

Applicant: XILINX, INC.

Inventor： Millind Mittal ,  Jaideep Dastidar ,  Kiran Puranik

IPC: H04L69/18

Abstract: Embodiments herein describe a layer converter that includes a proxy legacy interface that permits the layers for a legacy interconnect protocol to be recycled without any modifications, thus achieving legacy functionality alongside the new protocols' layer implementation. Put differently, the layer converter permits the layers of the legacy interconnect protocol to be reused to permit data to be transmitted on a link shared with data transmitted using a new interconnect protocol.

公开(公告)号：US11113194B2

公开(公告)日：2021-09-07

申请号：US16560217

申请日：2019-09-04

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  Millind Mittal

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/121

Abstract: The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.

公开(公告)号：US10673439B1

公开(公告)日：2020-06-02

申请号：US16367108

申请日：2019-03-27

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

公开(公告)号：US20200042446A1

公开(公告)日：2020-02-06

申请号：US16053488

申请日：2018-08-02

Applicant: Xilinx, Inc.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F12/0815

Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.