公开(公告)号：US20050154803A1

公开(公告)日：2005-07-14

申请号：US11009881

申请日：2004-12-10

Applicant: Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/28

CPC classification number: G06F13/102

Abstract: A method for accessing a memory of a computer system for BIOS codes optionally performs a detection procedure to realize a maximum memory burst read size of the memory according to a flag value upon the computer system is initialized. For example, the detection procedure is performed when the flag value is logic “1” and the detection procedure is not performed when the flag value is logic “0”. When the detection procedure is performed, read requests with sequentially reduced memory burst read sizes are asserted to the memory one by one until the maximum memory burst read size of the memory is realized. Then, the BIOS codes are read from the memory with the maximum memory burst read size.

Abstract translation: 用于访问用于BIOS代码的计算机系统的存储器的方法可选地执行检测过程，以在计算机系统初始化时根据标志值实现存储器的最大存储器突发读取大小。 例如，当标志值为逻辑“1”时执行检测过程，并且当标志值为逻辑“0”时不执行检测过程。 当执行检测过程时，依次减少的存储器突发读取大小的读取请求被逐个断言给存储器，直到实现存储器的最大存储器突发读取大小。 然后，从具有最大存储突发读取大小的存储器中读取BIOS代码。

公开(公告)号：US20050060617A1

公开(公告)日：2005-03-17

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US20120191961A1

公开(公告)日：2012-07-26

申请号：US13110098

申请日：2011-05-18

Applicant: Chin-Hwaun Wu ,  Chung-Ching Huang ,  Kuo-Han Chang ,  Tai-Yu Lin

Inventor： Chin-Hwaun Wu ,  Chung-Ching Huang ,  Kuo-Han Chang ,  Tai-Yu Lin

IPC: G06F12/06 ,  G06F9/06

CPC classification number: G06F9/4893 ,  G06F1/3275 ,  G06F1/329 ,  G06F9/461 ,  Y02D10/14 ,  Y02D10/24

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract translation: 提供了一种操作系统切换方法。 操作系统切换方法是用于包括控制单元，存储单元和存储单元的计算机系统，其中存储单元包括第一操作系统和第二操作系统。 该方法的步骤包括：分别将第一操作系统和第二操作系统加载到存储器单元的第一存储器空间和第二存储器空间中，并将第一存储器空间和第二存储器空间设置为工作状态， 分别为待机状态; 以及执行所述操作系统的第一切换，以及将所述第一存储器空间和所述第二存储器空间设置为待机状态和所述工作状态。

公开(公告)号：US20110307720A1

公开(公告)日：2011-12-15

申请号：US13115792

申请日：2011-05-25

Applicant: Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

Inventor： Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Abstract translation: 提供了一种计算机系统及其电源管理方法。 计算机系统具有图像读取模式，第一功率管理模式和第二功率管理模式，并且在第二功率管理模式下操作的计算机系统比在第一功率管理模式中消耗的功率消耗更少的功率。 计算机系统包括第一部分，包括图形处理单元，存储器空间和显示器; 以及第二部分，包括存储图像数据的存储器。 当计算机系统以图像读取模式操作时，图像数据已经从存储器传送到存储器空间，第二部分从第一电力管理模式进入第二电力管理模式，并且第一部分保持 在第一电源管理模式中，使得图形处理单元可以根据存储在存储器空间中的图像数据通过显示显示图像。

公开(公告)号：US07900028B2

公开(公告)日：2011-03-01

申请号：US11538693

申请日：2006-10-04

Applicant: Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

Inventor： Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

IPC: G06F9/00 ,  G06F9/24

CPC classification number: G06F13/385

Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Abstract translation: 在用于初始化共享总线的公共传输引擎的第一总线设备和第二总线设备的方法中，当第一总线设备的第一链路和第二总线设备的第二链路到公共传输引擎时，当第 计算机系统启动。 接下来，按顺序启用第一个链接和第二个链接。 然后，在建立到公共传输引擎的第一链路之后，发出来自第一总线设备的第一状态更新信号。 最后，在接收到第一状态更新信号并建立到公共传输引擎的第二链路之后，发出来自第二总线设备的第二状态更新信号。

公开(公告)号：US07809239B2

公开(公告)日：2010-10-05

申请号：US11268009

申请日：2005-11-07

Applicant: Lu-Kang Mao ,  Yu-Lin Chu ,  Chung-Ching Huang

Inventor： Lu-Kang Mao ,  Yu-Lin Chu ,  Chung-Ching Huang

IPC: H04N5/76

CPC classification number: H04N5/85 ,  G06F3/0489 ,  H04N5/4403 ,  H04N5/44582 ,  H04N21/42204 ,  H04N21/42646 ,  H04N21/4312 ,  H04N21/441 ,  H04N2005/4442

Abstract: In an electric appliance system, an electric appliance for performing designated functions and first and second remote controllers are included. The first remote controller is optionally triggered for controlling a first group of the designated functions, and the second remote controller is optionally triggered for controlling a second group of the designated functions. The second group includes at least one designated function included in the first group and at least one designated function excluded from the first group.

Abstract translation: 在电器系统中，包括用于执行指定功能的电器以及第一和第二遥控器。 可选地，第一遥控器被触发用于控制指定功能的第一组，并且可选地触发第二遥控器以控制第二组指定功能。 第二组包括包括在第一组中的至少一个指定功能和从第一组中排除的至少一个指定功能。

公开(公告)号：US20100205365A1

公开(公告)日：2010-08-12

申请号：US12416605

申请日：2009-04-01

Applicant: Chung-Ching Huang ,  Chin-Han Chang ,  Jia-Hung Wang

Inventor： Chung-Ching Huang ,  Chin-Han Chang ,  Jia-Hung Wang

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: A hard drive assessing method and a hard drive assessing system supporting a maximum transmission rate of a hard drive are provided, wherein the hard drive is accessed by a controller, and both the controller and the hard drive support a plurality of transmission rates. The maximum transmission rate of the hard drive is first obtained. When the controller reads data from the hard drive, the transmission rate of the controller is set to be not lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. When the controller writes data into the hard drive, the transmission rate of the controller is reduced to be lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. Thereby, the hard drive can be accessed at its maximum transmission rate.

Abstract translation: 提供了硬盘驱动器评估方法和支持硬盘驱动器的最大传输速率的硬盘驱动器评估系统，其中硬盘驱动器被控制器访问，并且控制器和硬盘驱动器都支持多个传输速率。 首先获得硬盘驱动器的最大传输速率。 当控制器从硬盘驱动器读取数据时，将控制器的传输速率设置为不低于最大传输速率，并将硬盘驱动器的传输速率保持在最大传输速率。 当控制器将数据写入硬盘驱动器时，控制器的传输速率降低到低于最大传输速率，硬盘驱动器的传输速率保持在最大传输速率。 因此，可以以其最大传输速率访问硬盘驱动器。

公开(公告)号：US07634672B2

公开(公告)日：2009-12-15

申请号：US11505973

申请日：2006-08-18

Applicant: Wen-Juin Huang ,  Chung-Ching Huang

Inventor： Wen-Juin Huang ,  Chung-Ching Huang

IPC: G06F1/26

CPC classification number: G06F1/3228

Abstract: A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Abstract translation: 提出了一种在具有来自外围设备的总线主机请求的非窥探睡眠状态下应用于中央处理单元的省电方法。 根据本发明，首先禁止中央处理单元取出指令。 然后驱动中央处理单元进入窥探休眠状态，并允许仲裁器将总线主控请求传送到中央处理单元。 中央处理单元完成总线主机请求后，仲裁器被禁止，中央处理单元被驱动离开窥探休眠状态并返回到非窥探睡眠状态。 因此，中央处理单元消耗的功率降低，从而节省功率。

公开(公告)号：US07554344B2

公开(公告)日：2009-06-30

申请号：US11622027

申请日：2007-01-11

Applicant: Chien-Ping Chung ,  Chung-Ching Huang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang

IPC: G01R27/08 ,  G01R31/08

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Apparatus and methods of adjusting system efficiency for a current-consuming system are disclosed. In the disclosed apparatus, a system current detector receives a system current from the current-consuming system and calculates a system current variation accordingly. A system efficiency adjustment module is coupled to the system current detector to receive the system current variation and output a frequency control signal and a voltage control signal accordingly.

Abstract translation: 公开了一种调节耗电系统效率的装置和方法。 在所公开的装置中，系统电流检测器从耗电系统接收系统电流并相应地计算系统电流变化。 系统效率调节模块耦合到系统电流检测器以接收系统电流变化并相应地输出频率控制信号和电压控制信号。

公开(公告)号：US07278035B2

公开(公告)日：2007-10-02

申请号：US10939573

申请日：2004-09-13

Applicant: Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: A system and method of real-time power management for use in computer systems. The system utilization is assessed by a North bridge, and a result is transferred to a South bridge. Thereafter, through transmitting sideband signals to a voltage controller and a frequency controller by sideband pins, the North Bridge provides faster and more efficient power management performance than the system management bus (SMBUS).

Abstract translation: 一种用于计算机系统的实时电源管理系统和方法。 系统利用率由北桥评估，结果转移到南桥。 此后，通过边带引脚将边带信号发送到电压控制器和频率控制器，北桥提供比系统管理总线（SMBUS）更快更有效的电源管理性能。