公开(公告)号：US20090325374A1

公开(公告)日：2009-12-31

申请号：US12556757

申请日：2009-09-10

申请人： Jung-Dal Choi ,  Yun-Seung Shin ,  Jong-Sun Sel

发明人： Jung-Dal Choi ,  Yun-Seung Shin ,  Jong-Sun Sel

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

摘要： Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

摘要翻译： 提供制造非易失性存储器件的方法。 在基板上形成隔离层。 衬底具有存储区和阱接触区，并且隔离层限定衬底的有源区。 在有源区上形成栅极绝缘层。 栅极绝缘层被图案化以在其中限定开口。 开口暴露衬底的阱接触区域的至少一部分，并且充当用于隔离层的后续蚀刻期间产生的电荷的电荷路径。 还提供了相关的存储器件。

公开(公告)号：US07397093B2

公开(公告)日：2008-07-08

申请号：US11241458

申请日：2005-09-30

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC分类号： H01L29/76

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

摘要翻译： 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US20080006872A1

公开(公告)日：2008-01-10

申请号：US11700315

申请日：2007-01-31

申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US20060234447A1

公开(公告)日：2006-10-19

申请号：US11403964

申请日：2006-04-13

申请人： Jung-Dal Choi ,  Yun-Seung Shin ,  Jong-Sun Sel

发明人： Jung-Dal Choi ,  Yun-Seung Shin ,  Jong-Sun Sel

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

摘要： Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

摘要翻译： 提供制造非易失性存储器件的方法。 在基板上形成隔离层。 衬底具有存储区和阱接触区，并且隔离层限定衬底的有源区。 在有源区上形成栅极绝缘层。 栅极绝缘层被图案化以在其中限定开口。 开口暴露衬底的阱接触区域的至少一部分，并且充当用于隔离层的后续蚀刻期间产生的电荷的电荷路径。 还提供了相关的存储器件。

公开(公告)号：US08329574B2

公开(公告)日：2012-12-11

申请号：US13230978

申请日：2011-09-13

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L21/44

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

公开(公告)号：US08198157B2

公开(公告)日：2012-06-12

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US20120045890A1

公开(公告)日：2012-02-23

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/28

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US07884425B2

公开(公告)日：2011-02-08

申请号：US12257939

申请日：2008-10-24

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.

摘要翻译： 在一个实施例中，半导体存储器件包括具有第一和第二有源区的衬底。 第一有源区包括第一源区和漏区，第二有源区包括第二源区和漏区。 第一层间电介质位于衬底上。 第一导电结构延伸穿过第一层间电介质。 第一位线位于第一层间电介质上。 第二层间电介质在第一层间电介质上。 接触孔延伸穿过第二和第一层间电介质。 该装置包括接触孔内的第二导电结构并且延伸穿过第一和第二层间电介质。 第二位线位于第二层间电介质上。 第二层间电介质的底部处的接触孔的宽度小于或基本上等于第二层间电介质顶部的宽度。

公开(公告)号：US07723776B2

公开(公告)日：2010-05-25

申请号：US11376371

申请日：2006-03-15

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

公开(公告)号：US20080079028A1

公开(公告)日：2008-04-03

申请号：US11648992

申请日：2007-01-03

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L27/10

CPC分类号： H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L28/20

摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.

摘要翻译： 通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅 在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上形成导电层，并且使导电层 以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。