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公开(公告)号：US20130320452A1
公开(公告)日：2013-12-05
申请号：US13486343
申请日：2012-06-01
申请人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。
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公开(公告)号：US20130234203A1
公开(公告)日：2013-09-12
申请号：US13415710
申请日：2012-03-08
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0886 , H01L29/45 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在工件中形成沟道区域，以及在沟道区域附近形成源极或漏极区域。 源极或漏极区包括包含SiP，SiA或硅化物的接触电阻降低材料层。 源极或漏极区域还包括包含SiCP或SiCAs的沟道应力材料层。
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33.发明申请公开(公告)号：US20110086491A1
公开(公告)日：2011-04-14
申请号：US12842546
申请日：2010-07-23
IPC分类号： H01L21/762
CPC分类号： H01L21/02546 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02639 , H01L21/76224 , H01L29/045 , H01L29/0665 , H01L29/66522
摘要： A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.
摘要翻译： 形成集成电路结构的方法包括提供具有硅衬底的晶片; 在硅衬底中形成多个浅沟槽隔离（STI）区域; 以及通过去除多个STI区域的相对侧壁之间的硅衬底的顶部来形成凹陷。 硅衬底中的所有凹部的基本上所有的长边在相同的方向上延伸。 然后在凹部中外延生长III-V族化合物半导体材料。
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34.发明申请High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio 有权具有改进的接通电流比的高移动性多栅极晶体管公开(公告)号：US20100252816A1
公开(公告)日：2010-10-07
申请号：US12639653
申请日：2009-12-16
CPC分类号： H01L29/8124 , H01L29/1054 , H01L29/122 , H01L29/66431 , H01L29/66484 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/812
摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.
摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。
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公开(公告)号：US08785285B2
公开(公告)日：2014-07-22
申请号：US13415710
申请日：2012-03-08
IPC分类号： H01L21/336
CPC分类号： H01L27/0886 , H01L29/45 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
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公开(公告)号：US08609518B2
公开(公告)日：2013-12-17
申请号：US13189119
申请日：2011-07-22
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.
摘要翻译： 形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。 在硅层上形成栅堆叠。 硅层凹陷以形成邻近栅堆叠的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。
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公开(公告)号：US20130020612A1
公开(公告)日：2013-01-24
申请号：US13189119
申请日：2011-07-22
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.
摘要翻译： 形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。 在硅层上形成栅堆叠。 硅层凹陷以形成邻近栅堆叠的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。
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公开(公告)号：US20120001239A1
公开(公告)日：2012-01-05
申请号：US12827709
申请日：2010-06-30
IPC分类号： H01L27/085 , H01L29/20
CPC分类号： H01L29/785 , H01L29/66795
摘要： A device includes a semiconductor substrate, and insulation regions in the semiconductor substrate. Opposite sidewalls of the insulation regions have a spacing between about 70 nm and about 300 nm. A III-V compound semiconductor region is formed between the opposite sidewalls of the insulation regions.
摘要翻译： 一种器件包括半导体衬底和半导体衬底中的绝缘区域。 绝缘区域的相对侧壁的间隔为约70nm至约300nm。 在绝缘区域的相对侧壁之间形成III-V族化合物半导体区域。
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39.发明申请公开(公告)号：US20110062492A1
公开(公告)日：2011-03-17
申请号：US12831852
申请日：2010-07-07
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02538 , H01L21/02639
摘要： An integrated circuit structure includes a semiconductor substrate formed of a first semiconductor material; two insulators in the semiconductor substrate; and a semiconductor region between and adjoining sidewalls of the two insulators. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material, and has a width less than about 50 nm.
摘要翻译： 集成电路结构包括由第一半导体材料形成的半导体衬底; 半导体衬底中的两个绝缘体; 以及在两个绝缘体的相邻侧壁之间的半导体区域。 半导体区域由与第一半导体材料不同的第二半导体材料形成，并且具有小于约50nm的宽度。
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公开(公告)号：US20100301392A1
公开(公告)日：2010-12-02
申请号：US12616002
申请日：2009-11-10
IPC分类号： H01L29/78 , H01L21/336 , H01L29/20
CPC分类号： H01L29/78 , H01L21/28264 , H01L29/4236 , H01L29/66462 , H01L29/66628 , H01L29/66863 , H01L29/7783 , H01L29/8128
摘要： A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.
摘要翻译： 一种形成集成电路结构的方法包括提供衬底，以及在衬底上外延生长第一半导体层。 第一半导体层包括由III族和V族元素形成的第一III-V族化合物半导体材料。 所述方法还包括在所述第一半导体层上形成栅极结构，以及在所述栅极结构的至少一个侧壁上形成栅极间隔物。 在形成栅极结构的步骤之后，在第一半导体层上外延生长包括第二III-V族化合物半导体材料的第二半导体层。
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