公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

Applicant: Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US20200006480A1

公开(公告)日：2020-01-02

申请号：US16024706

申请日：2018-06-29

Applicant: Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

Inventor： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US08609518B2

公开(公告)日：2013-12-17

申请号：US13189119

申请日：2011-07-22

Applicant: Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Cheng-Ying Huang

Inventor： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Cheng-Ying Huang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.

Abstract translation: 形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。 在硅层上形成栅堆叠。 硅层凹陷以形成邻近栅堆叠的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。

公开(公告)号：US20130020612A1

公开(公告)日：2013-01-24

申请号：US13189119

申请日：2011-07-22

Applicant: Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Cheng-Ying Huang

Inventor： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.

Abstract translation: 形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。 在硅层上形成栅堆叠。 硅层凹陷以形成邻近栅堆叠的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。

公开(公告)号：US20230090092A1

公开(公告)日：2023-03-23

申请号：US17448382

申请日：2021-09-22

Applicant: Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

Inventor： Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

IPC: H01L27/12 ,  H01L21/84

Abstract: An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

公开(公告)号：US20210202476A1

公开(公告)日：2021-07-01

申请号：US16728983

申请日：2019-12-27

Applicant: Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200098921A1

公开(公告)日：2020-03-26

申请号：US16143222

申请日：2018-09-26

Applicant: Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

Inventor： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.