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公开(公告)号:US08901665B2
公开(公告)日:2014-12-02
申请号:US13335431
申请日:2011-12-22
IPC分类号: H01L29/772 , H01L21/336
CPC分类号: H01L29/66545 , H01L21/28088 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66553 , H01L29/66795 , H01L29/785
摘要: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
摘要翻译: 本公开提供一种半导体制造方法,包括在半导体衬底上形成层间电介质(ILD)层。 ILD层具有由ILD层的侧壁限定的开口。 间隔元件形成在ILD层的侧壁上。 在与间隔元件相邻的开口中形成栅极结构。 在一个实施例中,侧壁间隔件还用于减小形成在开口中的门结构的尺寸(例如,长度)。
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公开(公告)号:US08703556B2
公开(公告)日:2014-04-22
申请号:US13599393
申请日:2012-08-30
IPC分类号: H01L21/00
CPC分类号: H01L29/66795 , H01L21/3065 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823864 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/41766 , H01L29/41791 , H01L29/6656 , H01L29/785 , H01L29/7851
摘要: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.
摘要翻译: 通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底和衬底上的翅片结构。 在前体中翅片结构的侧壁上形成侧壁间隔物。 翅片结构的一部分被凹入以形成具有侧壁间隔件作为其上部的凹陷沟槽。 在凹槽中外延生长半导体,并在凹陷沟槽上方持续生长以形成外延结构。
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公开(公告)号:US20130320452A1
公开(公告)日:2013-12-05
申请号:US13486343
申请日:2012-06-01
申请人: Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人: Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号: H01L27/088 , H01L21/336
CPC分类号: H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译: 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件,第一器件包括第一栅极结构,设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件,第二器件包括第二栅极结构,设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。
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公开(公告)号:US08872284B2
公开(公告)日:2014-10-28
申请号:US13425218
申请日:2012-03-20
IPC分类号: H01L29/78
CPC分类号: H01L29/7851 , H01L21/28556 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/7845 , H01L29/785
摘要: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
摘要翻译: 提供了一种用于鳍式场效应晶体管(FinFET)器件的栅极应力器。 闸应力器包括地板,第一应力侧壁和第二应力侧壁。 地板形成在栅极层的第一部分上。 栅极层设置在浅沟槽隔离(STI)区域的上方。 第一应力侧壁形成在栅极层的第二部分上。 栅极层的第二部分设置在散热片的侧壁上。 第二应力侧壁形成在栅极层的第三部分上。 栅极层的第三部分设置在与散热片间隔开的结构的侧壁上。 第一应力侧壁和第二应力侧壁不超过翅片的高度。
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公开(公告)号:US08759920B2
公开(公告)日:2014-06-24
申请号:US13486343
申请日:2012-06-01
申请人: Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人: Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号: H01L21/70
CPC分类号: H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译: 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件,第一器件包括第一栅极结构,设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件,第二器件包括第二栅极结构,设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。
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公开(公告)号:US20140061811A1
公开(公告)日:2014-03-06
申请号:US13599868
申请日:2012-08-30
IPC分类号: H01L27/092 , H01L21/28
CPC分类号: H01L21/28088 , H01L21/823842 , H01L21/823878 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.
摘要翻译: 本公开涉及集成电路制造,更具体地涉及金属栅极结构。 半导体器件的示例性结构包括:衬底,包括分离并围绕P活性区域和N-有源区域的隔离区域; P活性区域上的P-栅极结构中的P功函数金属层,其中所述P功函数金属层包括第一底部和第一侧壁,其中所述第一底部包括第一层金属化合物, 第一厚度 以及在所述N活性区域上的N-栅极结构中的N-功函数金属层,其中所述N-功函数金属层包括第二底部部分和第二侧壁,其中所述第二底部部分包括金属的第二层 化合物,其具有小于第一厚度的第二厚度。
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公开(公告)号:US09263277B2
公开(公告)日:2016-02-16
申请号:US13599868
申请日:2012-08-30
IPC分类号: H01L27/11 , H01L21/82 , H01L21/28 , H01L29/49 , H01L29/66 , H01L27/092 , H01L21/8238 , H01L29/51
CPC分类号: H01L21/28088 , H01L21/823842 , H01L21/823878 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.
摘要翻译: 本公开涉及集成电路制造,更具体地涉及金属栅极结构。 半导体器件的示例性结构包括:衬底,包括分离并围绕P活性区域和N-有源区域的隔离区域; P活性区域上的P-栅极结构中的P功函数金属层,其中所述P功函数金属层包括第一底部和第一侧壁,其中所述第一底部包括第一层金属化合物, 第一厚度 以及在所述N活性区域上的N-栅极结构中的N-功函数金属层,其中所述N-功函数金属层包括第二底部部分和第二侧壁,其中所述第二底部部分包括金属的第二层 化合物,其具有小于第一厚度的第二厚度。
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公开(公告)号:US20130249019A1
公开(公告)日:2013-09-26
申请号:US13425218
申请日:2012-03-20
IPC分类号: H01L29/78 , H01L21/285
CPC分类号: H01L29/7851 , H01L21/28556 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/7845 , H01L29/785
摘要: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
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公开(公告)号:US20130161762A1
公开(公告)日:2013-06-27
申请号:US13335431
申请日:2011-12-22
IPC分类号: H01L27/088 , H01L29/78 , H01L21/28
CPC分类号: H01L29/66545 , H01L21/28088 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66553 , H01L29/66795 , H01L29/785
摘要: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
摘要翻译: 本公开提供一种半导体制造方法,包括在半导体衬底上形成层间电介质(ILD)层。 ILD层具有由ILD层的侧壁限定的开口。 间隔元件形成在ILD层的侧壁上。 在与间隔元件相邻的开口中形成栅极结构。 在一个实施例中,侧壁间隔件还用于减小形成在开口中的门结构的尺寸(例如,长度)。
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