利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.016 秒)

    Semiconductor Device and Method of Forming the Same
    3.
    发明申请
    Semiconductor Device and Method of Forming the Same 有权
    半导体器件及其形成方法

    公开(公告)号：US20130320452A1

    公开(公告)日：2013-12-05

    申请号：US13486343

    申请日：2012-06-01

    申请人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

    发明人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。

    FinFET with metal gate stressor
    4.
    发明授权
    FinFET with metal gate stressor 有权
    FinFET与金属栅应力

    公开(公告)号：US08872284B2

    公开(公告)日：2014-10-28

    申请号：US13425218

    申请日：2012-03-20

    申请人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

    发明人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7851 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/7845 ,  H01L29/785

    摘要： A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

    摘要翻译： 提供了一种用于鳍式场效应晶体管（FinFET）器件的栅极应力器。 闸应力器包括地板，第一应力侧壁和第二应力侧壁。 地板形成在栅极层的第一部分上。 栅极层设置在浅沟槽隔离（STI）区域的上方。 第一应力侧壁形成在栅极层的第二部分上。 栅极层的第二部分设置在散热片的侧壁上。 第二应力侧壁形成在栅极层的第三部分上。 栅极层的第三部分设置在与散热片间隔开的结构的侧壁上。 第一应力侧壁和第二应力侧壁不超过翅片的高度。

    Semiconductor device and method of forming the same
    5.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08759920B2

    公开(公告)日：2014-06-24

    申请号：US13486343

    申请日：2012-06-01

    申请人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

    发明人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823814 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。

    Metal Gate Structure of a Semiconductor Device
    6.
    发明申请
    Metal Gate Structure of a Semiconductor Device 有权
    半导体器件的金属栅极结构

    公开(公告)号：US20140061811A1

    公开(公告)日：2014-03-06

    申请号：US13599868

    申请日：2012-08-30

    申请人： Pei-Shan Chien ,  Andrew Joseph Kelly

    发明人： Pei-Shan Chien ,  Andrew Joseph Kelly

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.

    摘要翻译： 本公开涉及集成电路制造，更具体地涉及金属栅极结构。 半导体器件的示例性结构包括：衬底，包括分离并围绕P活性区域和N-有源区域的隔离区域; P活性区域上的P-栅极结构中的P功函数金属层，其中所述P功函数金属层包括第一底部和第一侧壁，其中所述第一底部包括第一层金属化合物， 第一厚度 以及在所述N活性区域上的N-栅极结构中的N-功函数金属层，其中所述N-功函数金属层包括第二底部部分和第二侧壁，其中所述第二底部部分包括金属的第二层 化合物，其具有小于第一厚度的第二厚度。

    Metal gate structure of a semiconductor device
    7.
    发明授权
    Metal gate structure of a semiconductor device 有权
    半导体器件的金属栅极结构

    公开(公告)号：US09263277B2

    公开(公告)日：2016-02-16

    申请号：US13599868

    申请日：2012-08-30

    申请人： Pei-Shan Chien ,  Andrew Joseph Kelly

    发明人： Pei-Shan Chien ,  Andrew Joseph Kelly

    IPC分类号： H01L27/11 ,  H01L21/82 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.

    摘要翻译： 本公开涉及集成电路制造，更具体地涉及金属栅极结构。 半导体器件的示例性结构包括：衬底，包括分离并围绕P活性区域和N-有源区域的隔离区域; P活性区域上的P-栅极结构中的P功函数金属层，其中所述P功函数金属层包括第一底部和第一侧壁，其中所述第一底部包括第一层金属化合物， 第一厚度 以及在所述N活性区域上的N-栅极结构中的N-功函数金属层，其中所述N-功函数金属层包括第二底部部分和第二侧壁，其中所述第二底部部分包括金属的第二层 化合物，其具有小于第一厚度的第二厚度。