公开(公告)号：US11670505B2

公开(公告)日：2023-06-06

申请号：US17005542

申请日：2020-08-28

申请人： Vanguard International Semiconductor Corporation

发明人： Chih-Yen Chen

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L21/0243 ,  H01L21/0254 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/0242 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02513 ,  H01L29/2003 ,  H01L29/205

摘要： A semiconductor substrate is provided. The semiconductor substrate includes a ceramic base, a seed layer, and a nucleation layer. The ceramic base has a front surface and a back surface, and the front surface is a non-flat surface. The seed layer is disposed on the front surface of the ceramic substrate. The nucleation layer is disposed on the seed layer.

公开(公告)号：US20190172966A1

公开(公告)日：2019-06-06

申请号：US16261027

申请日：2019-01-29

申请人： Alan Chin ,  Cun-Zheng Ning

发明人： Alan Chin ,  Cun-Zheng Ning

IPC分类号： H01L31/18 ,  H01L31/046 ,  H01L31/0352

CPC分类号： H01L31/1896 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/3086 ,  H01L31/035281 ,  H01L31/046 ,  H01L31/184 ,  H01L31/1844 ,  Y02E10/544

摘要： Reusable nanostructured substrates for forming semiconductor thin films, such as those used in solar cells, are configured with nanopillars to permit improved lift-off of thin films.

公开(公告)号：US09876080B2

公开(公告)日：2018-01-23

申请号：US15218922

申请日：2016-07-25

申请人： IMEC VZW

发明人： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC分类号： H01L21/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/04 ,  H01L21/324 ,  H01L21/306 ,  H01L29/161 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

摘要： Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

公开(公告)号：US20170345654A1

公开(公告)日：2017-11-30

申请号：US15166825

申请日：2016-05-27

申请人： International Business Machines Corporation

发明人： Daniele Caimi ,  Lukas Czornomaz ,  Jean Fompeyrine ,  Emanuele Uccelli

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/32 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/02546 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02639 ,  H01L21/02645 ,  H01L29/20 ,  H01L29/32 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

公开(公告)号：US09685381B2

公开(公告)日：2017-06-20

申请号：US14777736

申请日：2013-06-28

申请人： Intel Corporation

发明人： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L21/8238 ,  H01L29/267 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795

摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

公开(公告)号：US20160189959A1

公开(公告)日：2016-06-30

申请号：US14585755

申请日：2014-12-30

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L21/823878 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/20

摘要： Forming a semiconductor device is disclosed, according to embodiments of the present disclosure. Forming the semiconductor device can include forming a first semiconductor layer directly on a silicon substrate. Forming the semiconductor device can include forming a second semiconductor layer directly on the first semiconductor layer and forming an insulating trench in the second semiconductor layer. Forming the semiconductor device can include removing the second portion of the second semiconductor layer, and forming a third semiconductor layer directly on the first semiconductor layer and adjacent to the insulating trench such that the first portion of second semiconductor layer is electrically insulated from the third semiconductor layer. The first semiconductor layer and the third semiconductor layer can each be a type III-V semiconductor and the second semiconductor layer can be a type IV semiconductor.

公开(公告)号：US09324853B2

公开(公告)日：2016-04-26

申请号：US14793772

申请日：2015-07-08

申请人： International Business Machines Corporation

发明人： Anirban Basu ,  Amlan Majumdar ,  Kuen-Ting Shiu ,  Yanning Sun

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/417

CPC分类号： H01L29/7787 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/28575 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/778 ,  H01L29/7784

摘要： A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.

公开(公告)号：US09129890B2

公开(公告)日：2015-09-08

申请号：US14449057

申请日：2014-07-31

申请人： International Rectifier Corporation

发明人： Michael A. Briere

IPC分类号： H01L29/20 ,  H01L21/02 ,  H01L29/36 ,  H01L29/66 ,  H01L29/778 ,  H01L29/15 ,  H01L29/205 ,  H01L29/10

CPC分类号： H01L29/2003 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02634 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/78

摘要： There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

摘要翻译： 这里公开了半导体结构和方法的各种实施方式。 半导体结构包括衬底，在衬底上的过渡体，以及具有在过渡体上方的底表面的III-V族中间体。 半导体结构还包括III-V族中间体顶表面上的III-V族元件层。 III-V族中间体具有连续降低的杂质浓度，其中底表面处的较高杂质浓度在顶表面上连续地降低到较低的杂质浓度。

公开(公告)号：US20150243773A1

公开(公告)日：2015-08-27

申请号：US14187708

申请日：2014-02-24

申请人： International Business Machines Corporation

发明人： Anirban Basu ,  Amlan Majumdar ,  Kuen-Ting Shiu ,  Yanning Sun

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/06 ,  H01L21/324 ,  H01L21/285 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7787 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/28575 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/778 ,  H01L29/7784

摘要： A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.

摘要翻译： 一种方法，包括沿着栅极沟槽的垂直侧壁形成一对内部间隔物，延伸到含III-V族化合物半导体的异质结构中的栅极沟槽，在栅极沟槽内形成栅极导体，去除第一介电层选择性的一部分 到栅极导体和一对内部间隔件，形成与该对内部间隔件相邻的一对外部间隔件，外部间隔件与内部间隔件直接接触并与其自对准，并且形成一对源极 -​​ 漏极 在含有III-V族化合物半导体的异质结构的最上层的接触点处，一对源极 -​​ 漏极接触件与该一对外部间隔物自对准，使得每个源极 - 漏极接触部分的边缘与外部边缘 。

公开(公告)号：US20150145001A1

公开(公告)日：2015-05-28

申请号：US14610254

申请日：2015-01-30

申请人： SEUNG-CHANG LEE ,  STEVEN R.J. BRUECK

发明人： SEUNG-CHANG LEE ,  STEVEN R.J. BRUECK

IPC分类号： H01L21/02 ,  H01L29/267 ,  H01L29/06

CPC分类号： H01L21/02513 ,  C30B7/005 ,  C30B23/025 ,  C30B25/04 ,  C30B25/18 ,  C30B25/183 ,  C30B29/40 ,  C30B29/42 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02636 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/0665 ,  H01L29/0688 ,  H01L29/267

摘要： Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

摘要翻译： 示例性实施例提供了使用晶格失配材料形成高质量半导体器件的材料和方法。 在一个实施方案中，包含一个或多个基本上单个颗粒的纳米颗粒层的复合膜可以沉积在衬底上作为纳米级选择性生长掩模，用于在衬底上外延生长晶格失配的材料。