公开(公告)号：US07257129B2

公开(公告)日：2007-08-14

申请号：US10045297

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J15/00 ,  G06F13/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US20070098112A1

公开(公告)日：2007-05-03

申请号：US11264303

申请日：2005-10-31

申请人： Gyudong Kim ,  Won Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Won Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

IPC分类号： H04L27/04 ,  H04B3/00

CPC分类号： H04L7/0008 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/4902

摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

摘要翻译： 电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。 信号发射器连接到通道。 信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。 信号接收器连接到通道。 信号接收器被配置为恢复直流平衡控制信号。

公开(公告)号：US20070002990A1

公开(公告)日：2007-01-04

申请号：US11498355

申请日：2006-08-02

申请人： Sang-Hyun Lee ,  Deog-Kyoon Jeong

发明人： Sang-Hyun Lee ,  Deog-Kyoon Jeong

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/081 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0037

摘要： A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. Data sampling phases are split so as to track the data eye. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare logic and generates phase control signals. These signals are set so as to control the sampling times of the data sampler and to attain near optimally recovered data stream. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.

摘要翻译： 用于串行数字数据链路的数据恢复系统包括数据采样器，比较逻辑，相位控制器和移相器。 数据采样器在一段时间内对输入数据进行三次采样，这个时间由移相器产生的时钟脉冲决定，并根据预定的判定标准恢复数字数据。 数据采样阶段被分割，以便跟踪数据的眼睛。 比较逻辑根据预定方法比较数据采样器的输出。 相位控制器使用比较逻辑的输出并产生相位控制信号。 这些信号被设置为控制数据采样器的采样时间并且获得接近最佳恢复的数据流。 移相器使用相位控制信号，并从输入时钟产生三个不同的相位时钟。 输入时钟可以是外部时钟，也可以从外部时钟或输入数据流中恢复。

公开(公告)号：US07154905B2

公开(公告)日：2006-12-26

申请号：US10035911

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J15/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07039121B2

公开(公告)日：2006-05-02

申请号：US10045393

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

公开(公告)号：US06976201B2

公开(公告)日：2005-12-13

申请号：US10036794

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J99/00 ,  G06F12/00 ,  G11C8/00 ,  H03M5/00 ,  H03M13/00 ,  H04J1/16 ,  H04J3/06 ,  H04J3/12 ,  H04J3/16 ,  H04J3/22 ,  H04L1/00 ,  H04L7/00 ,  H04L12/00 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture can provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture can also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，非对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如下面更详细地描述的 。 Storage Link架构还可以指定编码技术来优化转换并确保DC平衡。

公开(公告)号：US06891910B2

公开(公告)日：2005-05-10

申请号：US09759624

申请日：2001-01-12

申请人： Eunjoo Hwang ,  JongSang Choi ,  Deog-Kyoon Jeong

发明人： Eunjoo Hwang ,  JongSang Choi ,  Deog-Kyoon Jeong

IPC分类号： H04L7/033 ,  H04L7/02 ,  H04L25/03 ,  H04L7/00 ,  H03K7/40

CPC分类号： H04L7/0062 ,  H04L7/0058 ,  H04L2025/0349

摘要： A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are extracted only from filter coefficients of feed-forward and feedback filters. The relation between the coefficients of feed-forward filter and the impulse response is derived under a zero-forcing condition while the relation between the coefficients of the feedback filter and the impulse response is known. Based on the relations, several timing functions with varied degrees of computation are derived, which can drive the sampling instances approximately at the peak point of the channel impulse response. Since the derived timing functions use equalizer coefficients, they work jointly with equalization even without using a training sequence. Simulation results over 5-m and 100-m UTP Category-5 cables at 125M Baud show fast and robust timing recovery operation in a phase-locked loop.

摘要翻译： 公开了一种用于与判决反馈均衡器联合操作的简单且鲁棒的波特率定时恢复的系统和方法。 定时恢复的定时功能仅从前馈和反馈滤波器的滤波器系数提取。 前馈滤波器系数与脉冲响应之间的关系是在零强制条件下导出的，而反馈滤波器的系数与脉冲响应之间的关系是已知的。 基于关系，导出了具有不同程度的计算的几个定时函数，其可以在通道脉冲响应的峰值点处驱动采样实例。 由于导出的定时功能使用均衡器系数，所以即使不使用训练序列，它们也可以共同工作。 在125M波特的5m和100m UTP 5类电缆上的仿真结果显示了锁相环路中快速稳健的定时恢复操作。

公开(公告)号：US06781424B2

公开(公告)日：2004-08-24

申请号：US10253534

申请日：2002-09-25

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06512408B2

公开(公告)日：2003-01-28

申请号：US09985897

申请日：2001-11-06

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

公开(公告)号：US06483355B1

公开(公告)日：2002-11-19

申请号：US09709637

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。