公开(公告)号：US20070098112A1

公开(公告)日：2007-05-03

申请号：US11264303

申请日：2005-10-31

申请人： Gyudong Kim ,  Won Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Won Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

IPC分类号： H04L27/04 ,  H04B3/00

CPC分类号： H04L7/0008 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/4902

摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

摘要翻译： 电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。 信号发射器连接到通道。 信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。 信号接收器连接到通道。 信号接收器被配置为恢复直流平衡控制信号。

公开(公告)号：US07627044B2

公开(公告)日：2009-12-01

申请号：US11264303

申请日：2005-10-31

申请人： Gyudong Kim ,  Won Jun Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Won Jun Choe ,  Deog-Kyoon Jeong ,  Jaeha Kim ,  Bong-Joon Lee ,  Min-Kyu Kim

IPC分类号： H04B3/00

CPC分类号： H04L7/0008 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/4902

摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

摘要翻译： 电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。 信号发射器连接到通道。 信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。 信号接收器连接到通道。 信号接收器被配置为恢复直流平衡控制信号。

公开(公告)号：US6157360A

公开(公告)日：2000-12-05

申请号：US815486

申请日：1997-03-11

申请人： Deog-Kyoon Jeong ,  Gyudong Kim ,  Ho Young Song ,  David D. Lee

发明人： Deog-Kyoon Jeong ,  Gyudong Kim ,  Ho Young Song ,  David D. Lee

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G3/3696

摘要： Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps--the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns itself off when the analog voltage reaches the certain level. Also described are various column driver architectures in which buffers are placed in various ways in a column driver in between the resistor-string DAC and the column decoders in order to minimize the number of required buffers.

摘要翻译： 描述了一种使用电阻串数模转换器（DAC）驱动有源矩阵显示器列的系统和方法。 该描述包括以两步驱动模拟数据电压的自动停止缓冲电路 - 第一步是在输出达到一定水平之前由“死区放大器”进行主动缓冲，第二步用作无源导管 输出达到一定水平后。 当模拟电压达到一定水平时，死区放大器本身就会自动关闭。 还描述了各种列驱动器架构，其中缓冲器以各种方式放置在电阻器串DAC和列解码器之间的列驱动器中，以便使所需缓冲器的数量最小化。

公开(公告)号：US06560290B2

公开(公告)日：2003-05-06

申请号：US09234619

申请日：1999-01-20

申请人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： H04L2700

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

摘要： New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

摘要翻译： 使用新的非常高速的CMOS技术来实现以千兆位速度运行的CMOS驱动器。 这样的驱动器可以比使用GaAs或双极技术的驱动器更容易制造，并且还可以容易地与其他CMOS电路集成。 与具有外部端接的接收机相比，使用千兆位CMOS驱动器的通信系统可以另外包括具有片上终止的接收器，以在存在电感中的寄生电容的情况下显着减少失真。 此外，通信系统可以包括相位跟踪器和帧对准器。 相位跟踪器连续监视过采样数据中最频繁的转换边沿，使得接收机时钟的相位跟踪发送器时钟。 帧对准器包括逗号检测器，该逗号检测器使串行数据流中具有单个逗号字符的数据字能够即时同步。

公开(公告)号：US6144242A

公开(公告)日：2000-11-07

申请号：US148815

申请日：1998-09-04

申请人： Deog-Kyoon Jeong ,  Gyudong Kim ,  David D. Lee

发明人： Deog-Kyoon Jeong ,  Gyudong Kim ,  David D. Lee

IPC分类号： H04B3/04 ,  H04L25/08 ,  H03H11/26

CPC分类号： H04L25/085

摘要： Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

摘要翻译： 多个可控延迟降低了传输多个同步信号期间的EMI辐射。 每个可控延迟将受控的延迟引入正在传输的相应信号。 受控的延迟使得峰值频率处的多个信号的组合强度显着降低。 这导致在那些峰值频率下降低了EMI辐射。

公开(公告)号：US06600771B1

公开(公告)日：2003-07-29

申请号：US09234777

申请日：1999-01-20

申请人： Yongsam Moon ,  Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Yongsam Moon ,  Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： H04B169

CPC分类号： H04B1/707 ,  G06F1/04 ,  H04B15/00 ,  H04B15/04 ,  H04B2215/064

摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

摘要翻译： 新的扩频相位调制（SSPM）技术适用于数据和时钟信号。 SSPM技术比直接序列扩频（DSSS）技术更适合板级设计。 此外，SSPM可以与受控边缘速率信令组合以优于DSSS。

公开(公告)号：US06271816B1

公开(公告)日：2001-08-07

申请号：US09148583

申请日：1998-09-04

申请人： Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： G09G336

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2330/021 ,  G09G2330/023

摘要： Switches and capacitors are efficiently used to passively change the voltage level on column electrodes without active driving by the column driver circuit. This significantly reduces the power needed by the column driver circuit to drive voltages of alternating polarity onto the column electrodes. In this way, significant power is saved in both the pixel inversion and the row inversion schemes. The average power savings of various of the embodiments exceeds 50% compared with a simple conventional implementation of a column driver circuit. Another aspect similarly reduces the power used by the column driver circuit in the back plane switching scheme.

摘要翻译： 开关和电容器被有效地用于被动地改变列电极上的电压电平，而无需由列驱动电路进行有源驱动。 这显着地降低了列驱动电路所需的功率，以驱动交替极性的电压到列电极上。 以这种方式，在像素反转和行反转方案中节省了显着的功率。 与列驱动电路的简单常规实施方式相比，各种实施例的平均功率节省超过了50％。 另一方面类似地减少了在背面切换方案中列驱动电路所使用的功率。

公开(公告)号：US07295578B1

公开(公告)日：2007-11-13

申请号：US09954291

申请日：2001-09-12

申请人： James D. Lyle ,  Gyudong Kim ,  Min-Kyu Kim ,  Ken-Sue Tan ,  Paul Daniel Wolf ,  Long Van Pham ,  Russel A. Martin

发明人： James D. Lyle ,  Gyudong Kim ,  Min-Kyu Kim ,  Ken-Sue Tan ,  Paul Daniel Wolf ,  Long Van Pham ,  Russel A. Martin

IPC分类号： H04J3/06

CPC分类号： H04L7/0008 ,  G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/045 ,  G09G2370/047 ,  H03L7/1974 ,  H04J3/0632 ,  H04L25/05 ,  H04N21/4305 ,  H04N21/435

摘要： A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.

摘要翻译： 包括发射机，接收机和类似TMDS的链路的通信系统，其中视频数据和辅助数据从发射机发射到接收机，或者通过链路从发射机到接收机传输视频数据， 辅助数据从接收机发送到发射机（或从发射机到接收机，也可以从接收机发送到发射机），用于这种系统的发射机或接收机以及用于在这种系统中发送辅助数据和视频数据的方法 链接，使这样的辅助数据与这样的视频数据同步，并产生具有与发送辅助数据的速率非常相似的频率的时钟。 通常，辅助数据包括一个或多个音频数据流。 在一些实施例中，发射机通过视频时钟信道向接收机发送视频时钟，发射机和接收机中的至少一个将至少一个辅助数据流发射到发射机和接收机中的另一个，以及至少一个 发射机和接收机通过视频时钟信道发送辅助数据的至少一个辅助时钟。

公开(公告)号：US07231009B2

公开(公告)日：2007-06-12

申请号：US10371220

申请日：2003-02-19

申请人： Gyudong Kim ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Min-Kyu Kim

IPC分类号： H04L7/00

CPC分类号： H04L7/0012 ,  H04L7/0008

摘要： Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

摘要翻译： 通过使用时钟信号来确定外部时钟信号和第一内部采样时钟信号之间的相位差是否小于预先选择的值来获得关于外部时钟信号的相位的附加信息。 如果系统确定相位差小于预先选择的值，则一个实施例用具有与第一内部采样时钟信号选择的相位关系的第二内部采样时钟信号对入局数据进行采样，例如1/2的时钟周期 不相位 通过在外部时钟的有效边沿和内部采样时钟的有效边沿之间保持足够的相位差，该实施例提供了足够的建立/保持余量以避免子系统跨越异步边界接收数据的亚稳态或其他问题。

公开(公告)号：US09015509B2

公开(公告)日：2015-04-21

申请号：US13362930

申请日：2012-01-31

申请人： Gyudong Kim ,  Eungu Kim ,  Min-Kyu Kim ,  Daeyun Shim ,  Ravi Sharma ,  Myounghwan Kim ,  Jaeryon Lee

发明人： Gyudong Kim ,  Eungu Kim ,  Min-Kyu Kim ,  Daeyun Shim ,  Ravi Sharma ,  Myounghwan Kim ,  Jaeryon Lee

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3246 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

摘要翻译： 本发明的实施例通常涉及低功率待机模式控制电路。 装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。 该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为 为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。