公开(公告)号：US20070077697A1

公开(公告)日：2007-04-05

申请号：US11241574

申请日：2005-09-30

申请人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  H. C. Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  H. C. Cheng

IPC分类号： H01L21/8238 ,  H01L21/425 ,  H01L21/31

CPC分类号： H01L21/76 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/08

摘要： A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

摘要翻译： 在半导体衬底中形成半绝缘部分的方法提供了将半导体衬底上的硬掩模膜沉积到足以防止带电粒子穿过硬掩模的厚度。 硬掩模被图案化以产生开孔，在注入过程中带电粒子通过该开口进入衬底。 半绝缘部分可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。 带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

公开(公告)号：US20050083747A1

公开(公告)日：2005-04-21

申请号：US10689421

申请日：2003-10-20

申请人： Denny Tang ,  Wen-Chin Lin

发明人： Denny Tang ,  Wen-Chin Lin

IPC分类号： G11C5/14 ,  G11C7/02 ,  G11C11/16 ,  G11C11/56

CPC分类号： G11C5/147 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5634

摘要： A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.

摘要翻译： 多电平参考发生器具有多个非线性标准电阻元件，其中每个电阻元件被偏置在恒定电平以产生合成电平。 多电平参考发生器具有多个镜源。 每个反射镜源与多个电阻元件中的一个电阻元件相通，使得每个反射镜源从一个标准电阻元件接收合成电平，并提供所得电平的镜像复制。 多电平参考发生器具有多个参考电平组合电路。 参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路，以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。

公开(公告)号：US07599215B2

公开(公告)日：2009-10-06

申请号：US11840051

申请日：2007-08-16

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu Chen Cheng

IPC分类号： G11C11/15

CPC分类号： G11C11/16

摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.

摘要翻译： 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。 如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

公开(公告)号：US20050206469A1

公开(公告)日：2005-09-22

申请号：US10804899

申请日：2004-03-19

申请人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

发明人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

IPC分类号： H01L23/522 ,  H01P1/36

CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.

摘要翻译： 在微电子产品中使用的电容器采用第一电容器板层，其包括第一系列水平分离和互连的尖齿。 电容器电介质层将第一电容器板层与第二电容器板层分开。 第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。 使用自对准方法形成电容器，并且电容器介电层形成为蛇形形状。

公开(公告)号：US20080239794A1

公开(公告)日：2008-10-02

申请号：US11840051

申请日：2007-08-16

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.

摘要翻译： 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。 如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

公开(公告)号：US07349243B2

公开(公告)日：2008-03-25

申请号：US11379527

申请日：2006-04-20

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.

摘要翻译： 这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。 所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。 在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。

公开(公告)号：US20070247900A1

公开(公告)日：2007-10-25

申请号：US11379527

申请日：2006-04-20

申请人： Wen-Chin Lin ,  Denny Tang ,  H.C. Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  H.C. Cheng

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.

摘要翻译： 这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。 所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。 在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。

公开(公告)号：US07050290B2

公开(公告)日：2006-05-23

申请号：US10768916

申请日：2004-01-30

申请人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

发明人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

IPC分类号： H01G4/008 ,  H01G4/20

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.

摘要翻译： 实现了具有两个端子的新的电容器装置。 该器件包括覆盖衬底的多个第一导电线。 每个第一导线连接到电容器装置端子之一。 相邻的第一导线连接到相对的端子。 第一导线包括多个导电材料。 多个第二导线覆盖多个第一导线。 每个第二导线连接到电容器件端子中的一个。 相邻的第二导线连接到相对的端子。 覆盖任何第一导线的任何第二导线连接到相对的端子。 第二导线包括多个导电材料。 第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。 第二介电层位于第一导线和第二导线之间。

公开(公告)号：US20050168914A1

公开(公告)日：2005-08-04

申请号：US10768916

申请日：2004-01-30

申请人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

发明人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

IPC分类号： H01G4/228 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.

摘要翻译： 实现了具有两个端子的新的电容器装置。 该器件包括覆盖衬底的多个第一导电线。 每个第一导线连接到电容器装置端子之一。 相邻的第一导线连接到相对的端子。 第一导线包括多个导电材料。 多个第二导线覆盖多个第一导线。 每个第二导线连接到电容器件端子中的一个。 相邻的第二导线连接到相对的端子。 覆盖任何第一导线的任何第二导线连接到相对的端子。 第二导线包括多个导电材料。 第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。 第二介电层位于第一导线和第二导线之间。

公开(公告)号：US07554145B2

公开(公告)日：2009-06-30

申请号：US11610760

申请日：2006-12-14

申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

IPC分类号： H01L29/76

CPC分类号： H01L43/12 ,  H01L27/228

摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。