公开(公告)号：US20060012438A1

公开(公告)日：2006-01-19

申请号：US11160767

申请日：2005-07-07

申请人： Yu-Pin Chou ,  Chia-Liang Chiang

发明人： Yu-Pin Chou ,  Chia-Liang Chiang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891 ,  H03L7/093

摘要： A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.

摘要翻译： 锁相环包括用于根据参考信号和输入信号产生相位误差信号的相位/频率检测器，用于根据相位误差信号输出电压信号的电荷泵，用于输出输出的电压控制振荡器 根据电压信号对应于相位误差信号的信号，自适应调整单元，用于根据相位误差信号输出控制信号，以便在输出信号和相位误差信号之间形成非线性。

公开(公告)号：US20050001656A1

公开(公告)日：2005-01-06

申请号：US10609535

申请日：2003-07-01

申请人： Yu-Pin Chou

发明人： Yu-Pin Chou

IPC分类号： H03D13/00

CPC分类号： H03D13/003

摘要： A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

摘要翻译： 示出了一种数字分数相位检测器，其使用相位误差检测器基于参考时钟信号和反馈时钟信号之间的相位差产生相位误差信号。 量化器直接测量相位误差信号的脉冲宽度，并以数字形式输出该值。 通过直接测量相位误差信号，量化精度提高。 为了校准数字分数相位检测器，校准脉冲发生器产生已知持续时间的校准脉冲并将其传递给量化器。

公开(公告)号：US08471859B2

公开(公告)日：2013-06-25

申请号：US12692389

申请日：2010-01-22

申请人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

发明人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC分类号： G09G5/39 ,  G09G5/36 ,  G06F12/02 ,  H04N7/01

CPC分类号： H04N7/0105 ,  H04N7/0132

摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

摘要翻译： 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US08284871B2

公开(公告)日：2012-10-09

申请号：US12501959

申请日：2009-07-13

申请人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

发明人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

IPC分类号： H04L27/22

CPC分类号： H04L7/10 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/046 ,  H04L25/4908

摘要： A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

摘要翻译： 接收机包括 恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。 数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。 还公开了接收机的方法。

公开(公告)号：US07778321B2

公开(公告)日：2010-08-17

申请号：US11165029

申请日：2005-06-24

申请人： Yu-Pin Chou ,  Chao-Hsin Lu

发明人： Yu-Pin Chou ,  Chao-Hsin Lu

IPC分类号： H03K5/159

CPC分类号： H04L25/03019 ,  H04L2025/03764

摘要： A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

摘要翻译： 用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。 首先，检测发送信号中的第一频带和第二频带的信号强度。 然后比较第一频带和第二频带的信号强度以获得补偿比，即第一频带的总补偿量到第二频带。 最后，根据补偿比的反馈调整均衡器的参数设置。 因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

公开(公告)号：US20090153574A1

公开(公告)日：2009-06-18

申请号：US12275912

申请日：2008-11-21

申请人： Yu-Pin Chou ,  Tzou-Bo Lin ,  Chih-Ming Lee ,  Ming-Syun Wu

发明人： Yu-Pin Chou ,  Tzou-Bo Lin ,  Chih-Ming Lee ,  Ming-Syun Wu

IPC分类号： G09G5/39

CPC分类号： G09G5/003 ,  G09G5/006 ,  G09G2370/047

摘要： A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I2C auxiliary channel device servicer for receiving the output signal and generating an I2C protocol updated firmware, and a memory unit for updating firmware according to the I2C protocol updated firmware. A method for updating firmware is also disclosed.

摘要翻译： 通过DisplayPort接口更新固件的系统包括具有DisplayPort接口的源设备和具有DisplayPort接口的接收器设备。 源设备包括用于存储和提供更新的固件的存储电路，以及用于以辅助信道信号格式输出更新的固件的源设备辅助通道。 宿设备包括宿设备辅助通道，用于以辅助通道信号格式接收更新的固件，从而生成输出信号，用于接收输出信号并产生I2C协议更新固件的I2C辅助通道设备服务器，以及存储器单元 根据I2C协议更新固件更新固件。 还公开了一种用于更新固件的方法。

公开(公告)号：US20090153545A1

公开(公告)日：2009-06-18

申请号：US12314601

申请日：2008-12-12

申请人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

发明人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G5/005 ,  G09G2370/12

摘要： A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

摘要翻译： 一种用于显示处理装置的定时控制器包括：多个预定引脚，用于通过引脚分配方式接收图像信号，其中图像信号是第一格式图像信号或第二格式图像信号; 检测器，其耦合到所述预定引脚并且用于检测所述预定引脚中的至少一个以确定所述图像信号是所述第一格式图像信号还是所述第二格式图像信号，并输出检测结果; 以及耦合到所述检测器并用于根据所述检测结果来处理所述图像信号的处理器以产生和输出定时控制信号的处理器。

公开(公告)号：US07545222B2

公开(公告)日：2009-06-09

申请号：US11620053

申请日：2007-01-05

申请人： Yu-Pin Chou ,  Chi-Kung Kuan

发明人： Yu-Pin Chou ,  Chi-Kung Kuan

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/0814 ,  H03L7/0891 ,  H03L7/0991 ,  H03L7/0996 ,  H03L2207/06 ,  Y10S331/02

摘要： A phase-locked loop (PLL) for rapid lock-in applicable to digital, analog, or hybrid digital-analog PLL circuits is provided. Besides the units for basic operation, including a phase-frequency detector (PFD), a charge pump, a loop filter, and/or a voltage/current/digital-controlled oscillator (VCO/ICO/DCO), an additional lock-in actuator circuit is provided for providing lock-in signals, achieving the purpose of rapid lock-in through operational processes.

摘要翻译： 提供了一种用于快速锁定的锁相环（PLL），适用于数字，模拟或混合数字 - 模拟PLL电路。 除了用于基本操作的单元，包括相位频率检测器（PFD），电荷泵，环路滤波器和/或电压/电流/数字控制振荡器（VCO / ICO / DCO），附加锁定 致动器电路被提供用于提供锁定信号，实现通过操作过程快速锁定的目的。

公开(公告)号：US07532028B2

公开(公告)日：2009-05-12

申请号：US11863286

申请日：2007-09-28

申请人： Yu-Pin Chou

发明人： Yu-Pin Chou

IPC分类号： H03K17/16

CPC分类号： H03H7/40

摘要： The invention relates to an impedance matching circuit including: an input terminal for receiving an input signal; a variable impedance unit, coupled to the input terminal, having an equivalent impedance for providing the input terminal with an input impedance; a signal quality evaluating unit, coupled to the input terminal, for evaluating a signal quality of the input signal; and a control unit coupled to the variable impedance unit and the signal quality evaluating unit, for outputting a target control signal according to an evaluating result of the signal quality evaluating unit to adjust the equivalent impedance of the variable impedance unit.

摘要翻译： 本发明涉及一种阻抗匹配电路，包括：输入端，用于接收输入信号; 耦合到输入端的可变阻抗单元具有用于向输入端提供输入阻抗的等效阻抗; 信号质量评估单元，耦合到输入端，用于评估输入信号的信号质量; 以及耦合到所述可变阻抗单元和所述信号质量评估单元的控制单元，用于根据所述信号质量评估单元的评估结果输出目标控制信号，以调整所述可变阻抗单元的等效阻抗。

公开(公告)号：US20080079511A1

公开(公告)日：2008-04-03

申请号：US11863286

申请日：2007-09-28

申请人： Yu-Pin Chou

发明人： Yu-Pin Chou

IPC分类号： H03H7/40

CPC分类号： H03H7/40

摘要： The invention relates to an impedance matching circuit including: an input terminal for receiving an input signal; a variable impedance unit, coupled to the input terminal, having an equivalent impedance for providing the input terminal with an input impedance; a signal quality evaluating unit, coupled to the input terminal, for evaluating a signal quality of the input signal; and a control unit coupled to the variable impedance unit and the signal quality evaluating unit, for outputting a target control signal according to an evaluating result of the signal quality evaluating unit to adjust the equivalent impedance of the variable impedance unit.

摘要翻译： 本发明涉及一种阻抗匹配电路，包括：输入端，用于接收输入信号; 耦合到输入端的可变阻抗单元具有用于向输入端提供输入阻抗的等效阻抗; 信号质量评估单元，耦合到输入端，用于评估输入信号的信号质量; 以及耦合到所述可变阻抗单元和所述信号质量评估单元的控制单元，用于根据所述信号质量评估单元的评估结果输出目标控制信号，以调整所述可变阻抗单元的等效阻抗。