公开(公告)号：US07945706B2

公开(公告)日：2011-05-17

申请号：US12128634

申请日：2008-05-29

Applicant: An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

Inventor： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H04N5/4401 ,  H04N5/46 ,  H04N5/765 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/436 ,  H04N21/4363

Abstract: The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

Abstract translation: 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

公开(公告)号：US20100238159A1

公开(公告)日：2010-09-23

申请号：US12726931

申请日：2010-03-18

Applicant: Wen-Hsia KUNG ,  Tzuo-Bo LIN ,  Chia-Lung HUNG ,  Yu-Pin CHOU

Inventor： Wen-Hsia KUNG ,  Tzuo-Bo LIN ,  Chia-Lung HUNG ,  Yu-Pin CHOU

IPC: G06F3/038 ,  H03K3/00

CPC classification number: H03K5/151 ,  H03K19/0008

Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

Abstract translation: 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时，控制电路接收源信号并产生对应于第一模式的控制信号，并且当源信号符合第二预定义状态时，控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时，差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时，差分信号驱动器输出非差分信号输出。

公开(公告)号：US20100188574A1

公开(公告)日：2010-07-29

申请号：US12692389

申请日：2010-01-22

Applicant: Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

Inventor： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC: H04N9/64 ,  H04N5/04

CPC classification number: H04N7/0105 ,  H04N7/0132

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US20070201475A1

公开(公告)日：2007-08-30

申请号：US11674154

申请日：2007-02-13

Applicant: Kuo-Yang Li ,  Tzuo-bo Lin ,  Hsu-Jung Tung

Inventor： Kuo-Yang Li ,  Tzuo-bo Lin ,  Hsu-Jung Tung

IPC: H04L12/56

CPC classification number: H04N5/775 ,  H04L69/12 ,  H04N21/2389 ,  H04N21/4385 ,  H04N21/6332 ,  H04N21/654

Abstract: A packet processing system includes: a receiver for receiving a previous packet and a current packet through an interface; a storage device for storing the previous packet; a comparing module, coupled to the storage device and the receiver, for comparing contents of the current packet with contents of the previous packet to generate a comparison result; and a packet reading module, coupled to the storage device, for reading the contents of the current packet according to the comparison result.

Abstract translation: 分组处理系统包括：接收器，用于通过接口接收先前分组和当前分组; 用于存储先前分组的存储设备; 耦合到存储设备和接收器的比较模块，用于将当前分组的内容与先前分组的内容进行比较以产生比较结果; 以及分组读取模块，耦合到存储设备，用于根据比较结果读取当前分组的内容。

公开(公告)号：US20070174523A1

公开(公告)日：2007-07-26

申请号：US11306703

申请日：2006-01-09

Applicant: Tzuo-bo Lin ,  Hsu-Jung Tung ,  Sheng-Nan Chiou ,  Chia-Sheng Tsai

Inventor： Tzuo-bo Lin ,  Hsu-Jung Tung ,  Sheng-Nan Chiou ,  Chia-Sheng Tsai

IPC: G06F13/38

CPC classification number: G06F13/4295

Abstract: An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a current control word of a current data unit and a previous control word of a previous data unit; and a transmitter for generating the bitstream of the first digital interconnect format according to the sample words of the data units and the selected control words outputted from the decision unit.

Abstract translation: 公开了一种用于再生S / PDIF数据的装置和方法。 该装置包括用于缓冲数据单元的采样字的缓冲器; 决定单元，用于接收数据单元的控制字，并根据当前数据单元的当前控制字和先前数据单元的先前控制字输出所选择的控制字; 以及发送器，用于根据数据单元的采样字和从判定单元输出的所选择的控制字来产生第一数字互连格式的比特流。

公开(公告)号：US08810730B2

公开(公告)日：2014-08-19

申请号：US11937108

申请日：2007-11-08

Applicant: Hsu-Jung Tung ,  Tzuo-Bo Lin

Inventor： Hsu-Jung Tung ,  Tzuo-Bo Lin

IPC: H04N5/00 ,  H04N5/60 ,  H04N3/27 ,  H04N5/268 ,  H04N21/4402 ,  H04N21/439 ,  H04N21/44 ,  H04N5/44

CPC classification number: H04N5/44 ,  H04N21/4394 ,  H04N21/4396 ,  H04N21/44008 ,  H04N21/4402

Abstract: The invention relates to a receiving device for an audio-video system. The receiving device comprises a connector, a video processing unit, an audio processing module, and a monitoring unit. The monitoring unit detects a status of an inputted signal received by the connector and controls the operation of at lease one of the video processing unit and the audio processing module in accordance with the detected result to avoid the audio-video system display abnormal image or play noise when the receiving device did not receive the inputted signal by accident.

Abstract translation: 本发明涉及一种用于音视频系统的接收装置。 接收装置包括连接器，视频处理单元，音频处理模块和监视单元。 监视单元检测由连接器接收的输入信号的状态，并且根据检测结果控制视频处理单元和音频处理模块中的至少一个的操作，以避免音频 - 视频系统显示异常图像或播放 当接收设备没有意外地接收到输入信号时的噪声。

公开(公告)号：US08471859B2

公开(公告)日：2013-06-25

申请号：US12692389

申请日：2010-01-22

Applicant: Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

Inventor： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC: G09G5/39 ,  G09G5/36 ,  G06F12/02 ,  H04N7/01

CPC classification number: H04N7/0105 ,  H04N7/0132

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US08284871B2

公开(公告)日：2012-10-09

申请号：US12501959

申请日：2009-07-13

Applicant: Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

Inventor： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

IPC: H04L27/22

CPC classification number: H04L7/10 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/046 ,  H04L25/4908

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

Abstract translation: 接收机包括 恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。 数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。 还公开了接收机的方法。

公开(公告)号：US08258846B2

公开(公告)日：2012-09-04

申请号：US12876923

申请日：2010-09-07

Applicant: Tzuo-Bo Lin

Inventor： Tzuo-Bo Lin

IPC: H03K3/00

CPC classification number: H04L7/005

Abstract: A receiving method and apparatus is disclosed. The method comprising steps of: receiving a plurality of data according to a symbol clock signal, and reading out the plurality of data according to a first clock signal and generating a water level; receiving a second clock signal so as to generate a third clock signal, and adjusting the speed of the third clock signal according to the water level; determining a sampling frequency of the plurality of data according to a data amount of the plurality of data during a unit time period or parameters of the plurality of data; and dividing the third clock signal by a dividing value or multiplying the third clock signal by a multiplying value so as to obtain the first clock signal and adjust the water level by a clock generator.

Abstract translation: 公开了一种接收方法和装置。 该方法包括以下步骤：根据符号时钟信号接收多个数据，并根据第一时钟信号读出多个数据并产生一个水位; 接收第二时钟信号以产生第三时钟信号，并根据所述水位调节所述第三时钟信号的速度; 根据所述多个数据在单位时间段内的数据量或所述多个数据的参数，确定所述多个数据的采样频率; 并且将第三时钟信号除以分频值，或者将第三时钟信号乘以乘法值，以获得第一时钟信号，并通过时钟发生器调节水位。

公开(公告)号：US20090153545A1

公开(公告)日：2009-06-18

申请号：US12314601

申请日：2008-12-12

Applicant: Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

Inventor： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

IPC: G09G5/00

CPC classification number: G09G5/006 ,  G09G5/005 ,  G09G2370/12

Abstract: A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

Abstract translation: 一种用于显示处理装置的定时控制器包括：多个预定引脚，用于通过引脚分配方式接收图像信号，其中图像信号是第一格式图像信号或第二格式图像信号; 检测器，其耦合到所述预定引脚并且用于检测所述预定引脚中的至少一个以确定所述图像信号是所述第一格式图像信号还是所述第二格式图像信号，并输出检测结果; 以及耦合到所述检测器并用于根据所述检测结果来处理所述图像信号的处理器以产生和输出定时控制信号的处理器。