公开(公告)号：US07612405B2

公开(公告)日：2009-11-03

申请号：US11714644

申请日：2007-03-06

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

摘要翻译： 半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。 第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。 第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。 第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同 厚度

公开(公告)号：US20090096002A1

公开(公告)日：2009-04-16

申请号：US11872546

申请日：2007-10-15

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L2029/7858

摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。

公开(公告)号：US20080265338A1

公开(公告)日：2008-10-30

申请号：US11741580

申请日：2007-04-27

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US20080265321A1

公开(公告)日：2008-10-30

申请号：US11741602

申请日：2007-04-27

申请人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.

摘要翻译： 提供了具有改善的源极/漏极区域的鳍状场效应晶体管（finFET）。 在一个实施例中，去除鳍片的源极/漏极区域，同时留下与鳍片相邻的间隔物。 倾斜的注入用于在栅电极附近注入源极/漏极区，从而允许更均匀的轻掺杂漏极。 鳍可以通过外延生长或金属化过程重新形成。 在另一个实施例中，去除与源极/漏极区域中的鳍片相邻的间隔物，并且翅片沿翅片的侧面和顶部被硅化。 在另一个实施例中，在源极/漏极区域中去除鳍片和间隔物。 然后通过外延生长工艺或金属化工艺重新形成翅片。 也可以使用这些实施例的组合。

公开(公告)号：US08294201B2

公开(公告)日：2012-10-23

申请号：US13209493

申请日：2011-08-15

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L29/792

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。

公开(公告)号：US20080299754A1

公开(公告)日：2008-12-04

申请号：US11809337

申请日：2007-05-31

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

IPC分类号： H01L21/3205

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。 形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。 形成硅层的步骤包括原位掺杂第一杂质。 （或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

公开(公告)号：US20080194087A1

公开(公告)日：2008-08-14

申请号：US11729009

申请日：2007-03-28

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/3205 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/7834 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

公开(公告)号：US20080194072A1

公开(公告)日：2008-08-14

申请号：US11705655

申请日：2007-02-12

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

公开(公告)号：US20090047796A1

公开(公告)日：2009-02-19

申请号：US11837652

申请日：2007-08-13

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3115 ,  H01L21/3143

摘要： Nitridizing and optionally annealing plural high-k films layer-by-layer are performed to dope nitrogen into high-k films.

摘要翻译： 进行氮化并任选地对多个高k膜逐层退火以将氮掺杂到高k膜中。

公开(公告)号：US20090042381A1

公开(公告)日：2009-02-12

申请号：US11835263

申请日：2007-08-07

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/4763

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。