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    Method to form an embedded flash memory circuit with reduced process steps
    33.
    发明授权
    Method to form an embedded flash memory circuit with reduced process steps 有权
    用减少工艺步骤形成嵌入式闪存电路的方法

    公开(公告)号：US06380031B1

    公开(公告)日：2002-04-30

    申请号：US09637090

    申请日：2000-08-10

    申请人： Freidoon Mehrad ,  Jie Xia ,  Sandra Zheng ,  Lancy Tsung

    发明人： Freidoon Mehrad ,  Jie Xia ,  Sandra Zheng ,  Lancy Tsung

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L29/66825

    摘要： A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).

    摘要翻译： 描述了一种以缩短处理步骤形成嵌入式FLASH集成电路的方法。 在该方法中，对多晶硅膜（21）的控制栅极区域进行部分蚀刻。 然后使用多重蚀刻工艺同时形成闪存存储单元栅极堆叠（54），NMOS栅极结构（94）和PMOS栅极结构（96）。

    Nonvolatile memory array with compatible vertical source lines
    34.
    发明授权
    Nonvolatile memory array with compatible vertical source lines 失效
    具有兼容垂直源极线的非易失性存储器阵列

    公开(公告)号：US5659500A

    公开(公告)日：1997-08-19

    申请号：US533981

    申请日：1995-09-26

    申请人： Freidoon Mehrad

    发明人： Freidoon Mehrad

    IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L21/82

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A nonvolatile memory array has a plurality of diffused horizontal source lines (17), each source line (17) positioned between a pair of parallel horizontal stack conductors (ST). The plurality of the diffused horizontal source lines (17) are connected to at least one common vertical source conductor (17a). The common vertical source conductor (17a) includes continuous diffused regions (11) under each of said pair of parallel horizontal stack conductors (ST). In addition, the common vertical source conductor (17a) includes a metal conductor coupled to the continuous diffused regions at contacts (SC) located between the pairs of parallel horizontal stack conductors (ST). As a result, the stack conductors (ST) are straight. The straight-stack conductor (ST) configuration allows use of less space between a vertical source conductor (17a) and adjacent drain-column lines (18) and eliminates any need for use of vertical columns of dummy cells (10). Optional use of a straight-stack (ST) that is trimmed to a narrower width at the vertical source conductor (17a) results in a more certain conductive path under the straight stack conductors (ST).

    摘要翻译： 非易失性存储器阵列具有多个扩散的水平源极线（17），每个源极线（17）位于一对平行的水平叠层导体（ST）之间。 多个扩散水平源极线（17）连接到至少一个公共垂直源极导体（17a）。 公共垂直源极导体（17a）包括在所述一对平行水平叠层导体（ST）的下面的连续扩散区域（11）。 此外，公共垂直源极导体（17a）包括金属导体，其耦合到位于成对的平行水平叠层导体（ST）之间的触点（SC）处的连续扩散区域。 结果，堆叠导体（ST）是直的。 直堆叠导体（ST）构造允许在垂直源极导体（17a）和相邻的排列 - 列线（18）之间使用更少的空间，并且消除了使用虚拟电池（10）的垂直列的任何需要。 可选地使用在垂直源极导体（17a）处被调整到较窄宽度的直线堆叠（ST）导致直线堆叠导体（ST）下方更确定的导电路径。

    Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device
    35.
    发明授权
    Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device 有权
    用于促进半导体器件的多晶硅栅极和源极/漏极的同时硅化的结构

    公开(公告)号：US09035399B2

    公开(公告)日：2015-05-19

    申请号：US12731932

    申请日：2010-03-25

    申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

    发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

    摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

    Gate dielectric first replacement gate processes and integrated circuits therefrom
    37.
    发明授权
    Gate dielectric first replacement gate processes and integrated circuits therefrom 有权
    栅介质第一替代栅极工艺及其集成电路

    公开(公告)号：US07838356B2

    公开(公告)日：2010-11-23

    申请号：US12347197

    申请日：2008-12-31

    申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

    摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

    GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM
    38.
    发明申请
    GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM 有权
    门式电介质第一次更换门电路及集成电路

    公开(公告)号：US20100164006A1

    公开(公告)日：2010-07-01

    申请号：US12347197

    申请日：2008-12-31

    申请人： BRIAN K. KIRKPATRICK ,  Freidoon Mehrad ,  Shaofeng Yu

    发明人： BRIAN K. KIRKPATRICK ,  Freidoon Mehrad ,  Shaofeng Yu

    IPC分类号： H01L27/088 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

    摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

    REDUCING GATE CD BIAS IN CMOS PROCESSING
    40.
    发明申请
    REDUCING GATE CD BIAS IN CMOS PROCESSING 有权
    降低CMOS加工中的门偏移

    公开(公告)号：US20090166629A1

    公开(公告)日：2009-07-02

    申请号：US12241798

    申请日：2008-09-30

    申请人： Freidoon Mehrad ,  Jinhan Choi ,  Frank Scott Johnson

    发明人： Freidoon Mehrad ,  Jinhan Choi ,  Frank Scott Johnson

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/82385 ,  H01L21/823842

    摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

    摘要翻译： 公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。 该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。 该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层 。 该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。