公开(公告)号：US07894506B2

公开(公告)日：2011-02-22

申请号：US11767123

申请日：2007-06-22

Applicant: Mark Kent ,  Vinko Erceg ,  Jun Zheng

Inventor： Mark Kent ,  Vinko Erceg ,  Jun Zheng

IPC: H04L27/30

CPC classification number: H04B7/0417 ,  H04B7/0626 ,  H04B7/0639 ,  H04B7/0641

Abstract: Aspects of a method and system for a delta quantizer for MIMO pre-coders with finite rate channel state information feedback may include quantizing a change in channel state information in a MIMO pre-coding system onto a codebook, which comprises one or more unitary matrices, using a cost function. The codebook may be generated based on at least the channel state information. The channel state information may comprise a matrix V and the cost function f(A) may be defined by the following relationship: f ⁡ ( A ) = ( 1 N ⁢ ∑ j = 1 N ⁢  a jj  2 ) where A is a matrix of size N by N and aij is element (i,j) of matrix A. One or more unitary matrices may be generated from at least a first set of matrices and a second set of matrices, where the first set of matrices may comprise one or more Givens matrices. A dynamic range and a resolution of the codebook may be modified.

Abstract translation: 用于具有有限速率信道状态信息反馈的MIMO预编码器的Δ量化器的方法和系统的方面可以包括将MIMO预编码系统中的信道状态信息的变化量化到包括一个或多个酉矩阵的码本上， 使用成本函数。 码本可以至少基于信道状态信息生成。 信道状态信息可以包括矩阵V，并且成本函数f（A）可以由以下关系定义：f⁡（A）=（1NΣj = 1 Na jj钟2）其中A是 尺寸N乘N的矩阵和aij是矩阵A的元素（i，j）。可以从至少第一组矩阵和第二组矩阵生成一个或多个酉矩阵，其中第一组矩阵可以 包括一个或多个Givens矩阵。 可以修改码本的动态范围和分辨率。

公开(公告)号：US07856020B2

公开(公告)日：2010-12-21

申请号：US11548562

申请日：2006-10-11

Applicant: Ron Grinfeld

Inventor： Ron Grinfeld

IPC: H04L12/28

CPC classification number: H04L69/16 ,  G06Q40/04 ,  H04L69/161

Abstract: A transport protocol receiver for receiving a packet from a network, the packet having a header, payload, and connection context. The receiver includes an analysis engine, coupled to receive the packet from the network and adapted to parse and validate the header, locate the connection context, and generate a classification of the header. The receiver further includes a context processing engine, coupled to the analysis engine, and adapted to evaluate and update the connection context, responsive to the classification; and a data dispatch engine, coupled to the analysis engine and the context processing engine, and adapted to convey the payload to a destination, responsive to the connection context, such that the analysis engine, the context processing engine, and the data dispatch engine operate substantially asynchronously.

Abstract translation: 一种用于从网络接收分组的传输协议接收器，所述分组具有报头，有效载荷和连接上下文。 接收机包括一个分析引擎，它被耦合以从网络接收分组并且适于解析和验证报头，定位连接上下文，并产生报头的分类。 接收器还包括耦合到分析引擎的上下文处理引擎，并且适于响应于分类来评估和更新连接上下文; 以及耦合到分析引擎和上下文处理引擎的数据调度引擎​​，并且适于响应于连接上下文将有效负载传送到目的地，使得分析引擎，上下文处理引擎和数据调度引擎​​操作 基本上是异步的。

公开(公告)号：US07826470B1

公开(公告)日：2010-11-02

申请号：US11416817

申请日：2006-05-03

Applicant: Eliezer Aloni ,  Kobby Carmona ,  Shay Mizrachi ,  Rafi Shalom ,  Merav Sicron ,  Dov Hirshfeld ,  Amit Oren ,  Caitlin Bestler ,  Uri Tal

Inventor： Eliezer Aloni ,  Kobby Carmona ,  Shay Mizrachi ,  Rafi Shalom ,  Merav Sicron ,  Dov Hirshfeld ,  Amit Oren ,  Caitlin Bestler ,  Uri Tal

IPC: H02L12/28

CPC classification number: H04L49/9063 ,  H04L49/90

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract translation: 网络接口设备包括通过总线与主机处理器和存储器通信的总线接口，以及通过分组网络发送和接收承载数据的数据分组的网络接口。 协议处理器通过总线接口在网络接口和存储器之间传送数据，同时根据多个不同的应用程序流对数据包执行协议卸载处理。 总线接口对数据进行排队，以便在分配给不同应用流的多个队列中通过总线传输，并根据队列通过总线发送数据。

公开(公告)号：US07593707B2

公开(公告)日：2009-09-22

申请号：US10987977

申请日：2004-11-12

Applicant: Brima Ibrahim ,  Hea Joung Kim ,  Hooman Darabi

Inventor： Brima Ibrahim ,  Hea Joung Kim ,  Hooman Darabi

IPC: H04B1/06

CPC classification number: H04L25/061 ,  H03D3/008 ,  H03F1/34 ,  H03F2200/336 ,  H03F2200/375 ,  H03G3/001 ,  H03G3/3068 ,  H04B1/30 ,  H04L25/063 ,  H04L27/0002 ,  H04L27/364 ,  H04L27/366

Abstract: Aspects of compensating for DC offset in an RF receiver may comprise sampling data from at least one of a plurality of output paths, selecting a sampled data and generating at least one feedback signal based on the selected sampled data. The generated feedback signal may be fed back to at least one of a plurality of input paths, and at least one of the feedback signals may be of an opposite polarity to the selected sampled data. The selected sampled data may be converted to a digital sample, a plurality of the digital samples accumulated, and an average of the plurality of the digital samples calculated. A digital feedback value may be generated based on the average. A phase of the digital feedback value may be adjusted via a derotator, which may utilize the coordinate rotation digital computer (CORDIC) algorithm.

Abstract translation: 补偿RF接收机中的DC偏移的方面可以包括从多个输出路径中的至少一个采样数据，选择采样数据并基于所选择的采样数据生成至少一个反馈信号。 产生的反馈信号可以反馈到多个输入路径中的至少一个，并且至少一个反馈信号可能与所选择的采样数据具有相反的极性。 所选择的采样数据可以被转换成数字样本，多个数字样本被累积，并且计算出多个数字样本的平均值。 可以基于平均值生成数字反馈值。 数字反馈值的相位可以通过解旋器进行调整，该解旋器可以利用坐标旋转数字计算机（CORDIC）算法。

公开(公告)号：US07586636B2

公开(公告)日：2009-09-08

申请号：US11428700

申请日：2006-07-05

Applicant: Jeyhan Karaoguz ,  James D. Bennett

Inventor： Jeyhan Karaoguz ,  James D. Bennett

IPC: G06F15/00 ,  G06F15/16

CPC classification number: G06F3/1288 ,  G06F3/1203 ,  G06F3/1224

Abstract: Systems and methods of printer resource sharing in a communication network are provided. In one embodiment, the system may comprise, for example, at least one communication device, a communication network, print server software, and at least one personal printer resource. The communication device may be deployed at a location. The communication network may be communicatively coupled to that communication device. The print server software may receive from the communication device via the communication network a request for printing of information content. The print server software may respond by coordinating the printing of the information content. The at least one personal printer resource may be communicatively coupled to the at least one communication device. The print server software may reside outside of the at least one personal printer resource, and the at least one personal printer resource may be accessed for printing by the communication device via the communication network.

Abstract translation: 提供了通信网络中打印机资源共享的系统和方法。 在一个实施例中，系统可以包括例如至少一个通信设备，通信网络，打印服务器软件和至少一个个人打印机资源。 通信设备可以部署在一个位置。 通信网络可以通信地耦合到该通信设备。 打印服务器软件可以经由通信网络从通信设备接收对打印信息内容的请求。 打印服务器软件可以通过协调信息内容的打印来做出响应。 所述至少一个个人打印机资源可以通信地耦合到所述至少一个通信设备。 打印服务器软件可以驻留在至少一个个人打印机资源之外，并且可以访问至少一个个人打印机资源以供通信设备经由通信网络进行打印。

公开(公告)号：US06999735B2

公开(公告)日：2006-02-14

申请号：US10201130

申请日：2002-07-23

Applicant: Shahla Khorram

Inventor： Shahla Khorram

IPC: H04B17/00 ,  H03C1/62 ,  G01R19/00

CPC classification number: H03G3/3036

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has a gate, a drain, and a source, where the gate is coupled to the output of the amplifier, the source is coupled to a supply voltage, and the drain is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the drain of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract translation: 数字高频功率检测电路包括峰值检测电路和峰值计算电路。 峰值检测电路可操作地耦合以检测高频信号的峰值，并且包括放大器，晶体管和电容器。 放大器具有1μs输入和2输入输入，其中输入端1输入可操作地耦合以接收高频信号 。 晶体管具有栅极，漏极和源极，其中栅极耦合到放大器的输出端，源极耦合到电源电压，并且漏极耦合到第二和/ 放大器的输入。 电容器可操作地耦合到晶体管的漏极和参考电位。 电容施加的电压表示高频信号的峰值。 峰值计算电路可操作地耦合以从峰值产生数字峰值。

公开(公告)号：US06998877B2

公开(公告)日：2006-02-14

申请号：US10842608

申请日：2004-05-10

Applicant: Tsung-Hsien Lin

Inventor： Tsung-Hsien Lin

IPC: H03K19/20

CPC classification number: H03K19/09432

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output. The 2nd load is coupled to the drain of the complimentary transistor to provide a 2nd phase of the differential logic output.

Abstract translation: 一个高速差分信号逻辑门包括一个输入晶体管，第二输入晶体管，互补晶体管，电流源，第一输入晶体管，第二输入晶体管， 负载和2 负载。 第一输入晶体管可操作地耦合以接收第一差分输入信号的第一输入逻辑信号，其可以是第一差分输入信号的一相。 第二输入晶体管与第一输入晶体管并联耦合，并进一步耦合以接收第二输入逻辑信号，其中， 可以是差分输入信号的2相。 互补晶体管可操作地耦合到第一和第二和第二输入晶体管的源极并且接收互补输入信号，其模拟1 相位差分逻辑输出。 二极管负载耦合到互补晶体管的漏极以提供差分逻辑输出的第二相。

公开(公告)号：US06990143B2

公开(公告)日：2006-01-24

申请号：US10132856

申请日：2002-04-25

Applicant: Tsung-Hsien Lin

Inventor： Tsung-Hsien Lin

IPC: H04B17/00 ,  H04B3/46 ,  H04Q1/20

CPC classification number: H03K5/1565 ,  H03L7/0812

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract translation: 一种用于从参考时钟产生五十％占空比时钟的方法和装置。 该方法和装置包括边缘发生器，可控延迟模块，占空比控制环模块和复位电路。 边缘发生器被耦合以产生参考时钟的干净边缘。 可控延迟模块被耦合以基于占空比控制信号从干净边缘产生延迟边缘。 占空比控制环模块被耦合以基于延迟边沿和参考时钟信号产生占空比控制信号。 复位电路被耦合以复位边缘发生器以产生第二边缘。 第二边缘被可控延迟模块延迟以产生第二延迟边缘，使得延迟边缘和第二延迟边缘构成百分之五十占空比时钟的一个周期。

公开(公告)号：US06980789B2

公开(公告)日：2005-12-27

申请号：US10958916

申请日：2004-10-05

Applicant: Tsung-Hsien Lin

Inventor： Tsung-Hsien Lin

IPC: H03K17/041 ,  H03K23/66 ,  H03L7/18 ,  H03L7/197 ,  H03K3/289

CPC classification number: H03L7/18 ,  H03K17/04106 ,  H03K23/667 ,  H03L7/1976

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

Abstract translation: 用于振荡合成器的分频器模块包括多个触发器和逻辑电路。 多个触发器可互操作地耦合以产生基于控制信号的分频值。 逻辑电路可操作地耦合以基于分频器选择信号产生控制信号。 多个触发器中的每一个包括第一差分锁存模块，第二差分锁存模块。 第一差分锁存模块可操作地耦合以产生基于差分触发器输入信号的差分锁存信号。 第二差分锁存模块可操作地耦合以产生基于差分锁存信号的差分触发器输出。 第一和第二差分锁存模块中的每一个包括采样晶体管部分，保持晶体管部分，第一选通电路和第二门控电路。

公开(公告)号：US06980774B2

公开(公告)日：2005-12-27

申请号：US10103365

申请日：2002-03-21

Applicant: Hong Shi

Inventor： Hong Shi

IPC: H03L7/18 ,  H04B1/40 ,  H04B1/38

CPC classification number: H04B1/406 ,  H03L7/18

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation. The digital optimization module is operably coupled to the local oscillation module, the analog radio receiver and/or the analog radio transmitter to optimize performance of at least one aspect of the local oscillation module, the analog radio receiver and/or the analog radio transmitter for the given radio transceiving standard being implemented.

Abstract translation: 射频（RF）集成电路（IC）包括本地振荡模块，模拟无线电接收机，模拟无线电发射机，数字接收机模块，数字发射机模块和数字优化模块。 本地振荡模块可操作地耦合以产生至少一个本地振荡。 模拟无线电接收机可操作地耦合以基于本地振荡将入站RF信号直接转换成入站低中频信号。 数字接收机模块可操作地耦合以根据多个无线电收发标准之一处理入站低IF信号以产生入站数据。 数字发射机可操作地耦合以通过根据多个无线电收发标准之一处理出站数据来产生出站低中频信号。 模拟无线电发射机可操作地耦合以基于本地振荡将出站低IF信号直接转换为出站RF信号。 数字优化模块可操作地耦合到本地振荡模块，模拟无线电接收机和/或模拟无线电发射机，以优化本地振荡模块，模拟无线电接收机和/或模拟无线电发射机的至少一个方面的性能， 给定的无线电收发标准正在实施。