Abstract:
A source image with an input vertical resolution and an input horizontal resolution is received using an input clock signal. An intermediate image with an output vertical resolution and the input horizontal resolution is generated using an intermediate clock signal by scaling the source image. An output image with the output vertical resolution and an output horizontal resolution is generated using an output clock signal by scaling the intermediate image. The frequency of the intermediate clock signal is equal to the frequency of the output clock signal multiplied by the ratio of the input horizontal resolution to the output horizontal resolution.
Abstract:
TV tuners and methods thereof are provided. A TV tuner includes a first frequency converting circuit, a second frequency converting circuit, and a demodulator. The first frequency converting circuit, switchable between a first operating mode and a second operating mode, receives an RF signal and outputs a converted signal by performing high-side injection on the RF signal in the first operating mode and performing frequency addition on the RF signal in the second operating mode. The second frequency converting circuit performs a down conversion on the converted signal from the first frequency converting circuit to obtain an intermediate frequency signal. The demodulator demodulates the intermediate frequency signal and outputs a baseband frequency signal comprising video and audio signals.
Abstract:
A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.
Abstract:
An inverter has an inductor, a capacitor, a switching device, a driving circuit and a transformer. A first terminal of the capacitor is connected to the inductor, and the switching device is connected between the first terminal of the capacitor and a ground terminal. The driving circuit is connected to the switching device, wherein the driving circuit is arranged to control the switching device to turn on or turn off; and a primary side of the transformer is connected between a second terminal of the capacitor and the ground terminal.
Abstract:
In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.
Abstract:
A method for writing data into the memory, especially a method of preventing the data from overwriting for the write operation, is disclosed. The invention provides a control device for a memory system, which utilizes at least two layers of latches to hold the inputted data from a data bus and the data which prepares to be written into memory respectively. According to the control of communication between two layers of latches by the control device, the new inputted data of the succeeding write operation will not overwrite the data of the current write operation, thereby reducing the limitation for the cycle of writing (CYCW) and increasing the write speed.
Abstract:
A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.
Abstract:
An organic light emitting display (OLED) panel has a plurality of organic light emitting diodes. The organic light emitting diodes are electrically connected to a plurality of segment lines and a plurality of common lines in a matrix structure. The organic light emitting diodes electrically connected to the same common lines are divided into a first group and a second group. Driving currents are separately supplied to the organic light emitting diodes of the first group and the second group according to a first pulse width modulation (PWM) manner and a second PWM manner. The first PWM manner and the second PWM manner have complementary waveforms in a period.
Abstract:
A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.
Abstract:
A structure for preventing leakage of a high voltage device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.