公开(公告)号：US07953721B1

公开(公告)日：2011-05-31

申请号：US11963041

申请日：2007-12-21

Applicant: Gary Depelteau ,  David Walter Carr

Inventor： Gary Depelteau ,  David Walter Carr

IPC: G06F17/30

CPC classification number: G06F17/30327

Abstract: Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).

Abstract translation: 操作搜索引擎设备的方法包括从搜索引擎设备内的数据库重复读取下一个密钥（和相关联的句柄），以便将数据库的一些或可能全部的内容识别并传送到另一设备（例如，命令主机） 请求数据库内容。 读取下一个密钥的操作包括：（i）用第一密钥搜索搜索引擎设备内的流水线数据库，以识别大于第一密钥的至少一个密钥，然后（ii）执行下一个密钥获取操作 在流水线数据库中，从至少一个密钥识别下一个密钥。 然后从搜索引擎设备检索下一个密钥和与下一个密钥相关联的句柄（例如，传送到命令主机）。

公开(公告)号：US07924590B1

公开(公告)日：2011-04-12

申请号：US12844235

申请日：2010-07-27

Applicant: Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Alexei Starovoitov ,  Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C15/00

CPC classification number: G06F8/427 ,  G11C15/00

Abstract: A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.

Abstract translation: 内容搜索系统包括CAM设备，编译器和图像加载器。 包括多行CAM单元的CAM设备和通过可编程互连结构（PRS）选择性互连的多个计数器电路执行正则表达式搜索操作。 编译器选择性地将正则表达式转换成多个不同的位组，并且图像加载器将对应的位组加载到CAM单元中，并将其加载到多个控制PRS的配置的存储器元件中并进入计数器电路。

公开(公告)号：US07920398B1

公开(公告)日：2011-04-05

申请号：US12887267

申请日：2010-09-21

Applicant: Sandeep Khanna ,  Bindiganavale S. Nataraj ,  Chetan Deshpande ,  Vinay Iyengar

Inventor： Sandeep Khanna ,  Bindiganavale S. Nataraj ,  Chetan Deshpande ,  Vinay Iyengar

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/12

Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.

Abstract translation: 一种具有任意行数的内容可寻址存储器（CAM）器件，每行包括连接到多个CAM单元的匹配线，匹配线检测器电路和预充电电路。 检测器电路检测匹配线的电压，并基于检测到的匹配线电压产生反馈信号。 预充电电路响应于反馈信号自适应地对匹配线进行充电。

公开(公告)号：US07881125B2

公开(公告)日：2011-02-01

申请号：US12873122

申请日：2010-08-31

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

公开(公告)号：US07872890B1

公开(公告)日：2011-01-18

申请号：US12538852

申请日：2009-08-10

Applicant: Alexey Starovoytov

Inventor： Alexey Starovoytov

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A counter circuit is configured to simultaneously maintain individual character match count values for a plurality of overlapping substrings of an input string of characters that match a portion of a regular expression stored in a plurality of rows of content addressable memory (CAM) cells of a ternary CAM device. The counter circuit is selectable between a normal operational mode in which all matching portions of the input string are identified, and a minimum match length operational mode in which only matching portions of the input string that have at least a specified minimum number of characters are identified.

Abstract translation: 计数器电路被配置为同时维护与存储在三行内容可寻址存储器（CAM）单元的多行中的正则表达式的一部分匹配的输入字符串的多个重叠子串的单独字符匹配计数值 CAM设备。 计数器电路可在其中识别输入串的所有匹配部分的正常操作模式和最小匹配长度操作模式之间进行选择，其中仅识别具有至少指定的最小字符数的输入串的匹配部分 。

公开(公告)号：US20100318703A1

公开(公告)日：2010-12-16

申请号：US12815092

申请日：2010-06-14

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20100254709A1

公开(公告)日：2010-10-07

申请号：US12716094

申请日：2010-03-02

Applicant: Paolo Narvaez ,  Murat Bog

Inventor： Paolo Narvaez ,  Murat Bog

IPC: H04J14/08 ,  G06F12/00

CPC classification number: H04L49/552 ,  H04J3/062 ,  H04J3/12 ,  H04J3/1611 ,  H04J3/1617 ,  H04J2203/0069 ,  H04J2203/0085 ,  H04J2203/0094 ,  H04L12/54 ,  H04L49/351

Abstract: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

Abstract translation: 提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，所述系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。 该系统还包括LCAS控制管理器，该LCAS控制管理器被配置为响应于从数据对准器输入的数据而产生解排序控制命令。 该系统还包括解调器，其被配置为根据从LCAS控制管理器接收的去排序控制命令来对从数据对准器输入的输入数据进行排序。

公开(公告)号：US07797509B2

公开(公告)日：2010-09-14

申请号：US11652827

申请日：2007-01-11

Applicant: Gaurav Singh ,  Dave Hass ,  Daniel Chen

Inventor： Gaurav Singh ,  Dave Hass ,  Daniel Chen

IPC: G06F12/08

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract translation: 呈现用于将虚拟地址转换成物理地址的扩展翻译后备缓冲器（eTLB），eTLB包括具有多个物理地址的物理存储器地址存储器，虚拟存储器地址存储器，被配置为存储对应的多个虚拟存储器地址 物理地址，虚拟存储器地址存储包括集合关联存储器结构（SAM）和内容可寻址存储器（CAM）结构; 以及用于确定所请求的地址是否存在于所述虚拟存储器地址存储器中的比较电路，其中所述eTLB被配置为接收用于识别所述SAM结构和所述CAM结构的索引寄存器，并且其中所述eTLB被配置为接收用于 提供与所述多个虚拟存储器地址对应的虚拟页码。

公开(公告)号：US07783654B1

公开(公告)日：2010-08-24

申请号：US11533204

申请日：2006-09-19

Applicant: Sanjay Sreenath

Inventor： Sanjay Sreenath

IPC: G06F17/30 ,  G11C15/00

CPC classification number: G11C15/00

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. For one embodiment, the method includes selecting character groups from an input text string in a temporal sequence, each character group having more than one character. A first character group of the character groups is compared with a plurality of character fields and a current state of a state machine is compared with a plurality of states of the state machine that correspond to the plurality of character fields to identify information indicative of a subsequent state of the state machine. Comparison of the first character group with the plurality of sets of character fields is repeated if the information indicative of the subsequent state of the state machine indicates that a terminal number of characters of a desired character pattern has been located and that the terminal number of characters is fewer than the number of characters in the first character group.

Abstract translation: 一种使用三元内容可寻址存储器进行多字符串搜索的方法和装置。 对于一个实施例，该方法包括以时间顺序从输入文本串中选择字符组，每个字符组具有多于一个字符。 将字符组的第一字符组与多个字符字段进行比较，并将状态机的当前状态与对应于多个字符字段的状态机的多个状态进行比较，以识别指示后续字符的信息 状态机状态。 如果指示状态机的后续状态的信息指示所期望的字符模式的字符的终端数已经被定位，并且字符的终端数量，则重复第一字符组与多组字符字段的比较 小于第一个字符组中的字符数。

公开(公告)号：US07685480B1

公开(公告)日：2010-03-23

申请号：US11764668

申请日：2007-06-18

Applicant: Horng-jyi Fuh

Inventor： Horng-jyi Fuh

IPC: G11C29/26 ,  G11C29/50

CPC classification number: G11C29/816 ,  G11C15/00

Abstract: A system and method are provided for reducing the capacitive coupling noise on a fuse line of a content addressable memory (CAM) system. The CAM system includes a plurality of CAM arrays having a plurality of rows of CAM cells to store data coupled to wordlines, searchlines, bitlines and matchlines for reading from, writing to, and searching data in the CAM cells and a hit circuit coupled to the matchlines of each of the plurality of CAM arrays, the hit circuit to compare the data stored in the CAM cells against data presented on the wordlines of the CAM array.

Abstract translation: 提供了一种用于减小内容可寻址存储器（CAM）系统的熔丝线上的电容耦合噪声的系统和方法。 CAM系统包括多个具有多个CAM单元阵列的CAM阵列，以存储耦合到字线，搜索线，位线和匹配线的数据，用于在CAM单元中读取，写入和搜索数据，以及耦合到 所述多个CAM阵列中的每一个的匹配线，所述命中电路将存储在所述CAM单元中的数据与所述CAM阵列的字线上呈现的数据进行比较。