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公开(公告)号：US4998072A
公开(公告)日：1991-03-05
申请号：US482290
申请日：1990-02-20
Applicant: Tzafrir Sheffer
Inventor： Tzafrir Sheffer
CPC classification number: G06F1/0328
Abstract: The frequency resolution of a direct digital synthesizer is increased by varying the phase increment used to accumulate wave lookup table addresses between two integer values. The time periods during which the larger integer value is employed is proportional to a fractional part of the desired phase increment for providing an analog output at a selected frequency.
Abstract translation: 直接数字合成器的频率分辨率通过改变用于在两个整数值之间积累波形查找表地址的相位增量来增加。 使用较大整数值的时间段与用于在选定频率处提供模拟输出的期望相位增量的分数部分成比例。
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32.发明授权Phase accumulator with dithered incrementing of accumulation due to fine phase components 失效相位累加器由于细相分量而产生抖动增加的积累
公开(公告)号：US4984186A
公开(公告)日：1991-01-08
申请号：US398703
申请日：1989-08-25
Applicant: Karl E. Moerder
Inventor： Karl E. Moerder
CPC classification number: G06F1/0328 , G06F2211/902
Abstract: A phase accumulator for accumulating digital frequency words, which, as accumulated, represent the phase of a cyclic waveform of a predetermined frequency. The phase accumulator includes a coarse-component accumulator for accumulating coarse phase components of the digital frequency words; a fine-component accumulator for accumulating fine phase components of the digital frequency words; and means for incrementing the coarse-component accumulator in response to accumulation of the fine phase components. The incrementing means include means for providing a variable randomly generated value for each fine-component accumulation cycle; means for periodically sampling the accumulation of the fine phase components in relation to the randomly generated value; and means for incrementing the coarse component register for each fine-component accumulation cycle, with the phase of said incrementing being dithered in accordance with the number of times the accumulated fine phase components exceed the randomly generated values during the sampling period.
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公开(公告)号：US4773022A
公开(公告)日：1988-09-20
申请号：US697563
申请日：1985-02-01
Applicant: John F. Melville , Richard H. Weil
Inventor： John F. Melville , Richard H. Weil
CPC classification number: G06F1/0328
Abstract: An electrical waveform generator provides a memory for storing a plurality of data points representing sequential amplitude values of a desired waveform, a digital-to-analog converter for converting the data points to analog voltages for generating the desired waveform and apparatus for selectively coupling the data points to the converter, including apparatus for selecting groups of data points and for selectively looping through the groups.
Abstract translation: 电波形发生器提供用于存储表示期望波形的顺序振幅值的多个数据点的存储器，用于将数据点转换为模拟电压以产生期望波形的数模转换器，用于选择性地耦合数据 指向转换器，包括用于选择数据点组并用于选择性地循环通过组的装置。
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公开(公告)号：US4164020A
公开(公告)日：1979-08-07
申请号：US900883
申请日：1978-04-28
Applicant: Robert C. Griffith
Inventor： Robert C. Griffith
CPC classification number: G06F1/0328
Abstract: A programmable sound synthesizer, controlled by a microprocessor, can be fabricated according to the present invention to provide arbitrary programmability with respect to the waveform of an audible tone, frequency, amplitude, envelope shape of the wave train, including attack, sustain and the decay intervals of the envelope, rest or space intervals between notes as well as arbitrary selection of the note within an ordered sequence. A plurality of binary numbers, which in sequence are indicative of the waveform of the tone to be generated, can be read from a memory at a rate which defines the frequency of the waveform. The memory is read by an address generator whose repetition rate is controlled by an integrater. The rate of integration is in turn controlled by a tone number which is programmed into an appropriate register coupled to the integrater. Envelope and amplitude information may also be programmed into corresponding registers. The waveform memory, envelope register and amplitude register are each coupled to the central processor and read synchronously to generate the complex selected tone.
Abstract translation: 可以根据本发明制造由微处理器控制的可编程声音合成器，以提供关于波段的声音，频率，幅度，包络形状的波形的任意可编程性，包括攻击，维持和衰减 音符之间的间隔，音符间的间隔或间隔，以及有序序列内的音符的任意选择。 可以以限定波形频率的速率从存储器读取依次表示要生成的音调的波形的多个二进制数。 存储器由重复率由积分器控制的地址发生器读取。 积分速率又由一个音调编号控制，音调编程被编程到耦合到积分器的适当寄存器中。 信封和幅度信息也可编程到相应的寄存器中。 波形存储器，包络寄存器和振幅寄存器各自耦合到中央处理器并同步读取以产生复合选择的音调。
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公开(公告)号：US3716843A
公开(公告)日：1973-02-13
申请号：US3716843D
申请日：1971-12-08
Applicant: SANDERS ASSOCIATES INC
CPC classification number: G06F7/00 , G06F1/0328 , H03B21/025
Abstract: A modular signal processor which is assembled from a set of modules which have common input and output timing specifications such that any one module can be interconnected with any other module to perform a desired signal processing operation under the control of a timing generator. The timing generator is arranged to produce a clock signal of relatively high frequency and sequences of timing signals at a relatively lower frequency. Data is loaded into a module in response to a first one of the timing signal. The module then performs its operation or function upon the data to provide a result data. The result data is then read from the module in response to a subsequently occurring timing signal which is also employed to load the result data into another module. Specifically disclosed herein is a frequency synthesizer processor which employs the following modules: binary coded decimal to binary converter, phase accumulator, look up table and a digital to analog converter and filter.
Abstract translation: 一种模块化信号处理器，其由具有公共输入和输出定时规范的一组模块组装，使得任何一个模块可以与任何其他模块互连，以在定时发生器的控制下执行期望的信号处理操作。 定时发生器被布置成产生相对较高频率的时钟信号和相对较低频率的定时信号序列。 响应于定时信号中的第一个，将数据加载到模块中。 该模块然后对数据执行其操作或功能以提供结果数据。 然后响应于随后发生的定时信号从模块读取结果数据，其也用于将结果数据加载到另一模块中。 本文具体公开的是采用以下模块的频率合成器处理器：二进制编码的十进制到二进制转换器，相位累加器，查找表和数模转换器和滤波器。
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Patent Agency Ranking
公开(公告)号：US3610805A
公开(公告)日：1971-10-05
申请号：US3610805D
申请日：1969-10-30
Applicant: NORTH AMERICAN ROCKWELL
Inventor： WATSON GEORGE A , DEUTSCH RALPH
CPC classification number: G10H7/04 , G06F1/02 , G06F1/0328 , G10H1/0575 , G10H1/182 , G10H1/20
Abstract: In an electronic organ, the actuation of keys in accordance with corresponding audible tones to be reproduced effects the gating of pulses into time slots of a time division multiplexed signal, the time slots of the multiplexed signal being structured in accordance with a desired assignment sequence to correspond to the keys and to be representative thereof for identifying each note capable of being generated by the organ. A set of note, or tone, generators with availability assignment control means for capturing a pulse in the multiplexed signal are each rendered responsive to a given captured pulse for generating the tone represented by that pulse. The appropriate tone is generated digitally in the form of amplitude samples of a waveform stored in a memory, and the amplitude samples are subsequently subjected to digital-to-analog conversion for ultimate production of the audible output of the organ. Attack and decay of the tone, or note, waveform envelope are simulated by appropriately scaling the amplitude samples at the leading and trailing portions of the waveform envelope.
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37.发明授权公开(公告)号：US10061344B2
公开(公告)日：2018-08-28
申请号：US14901163
申请日：2014-06-02
Applicant: Endress + Hauser GmbH + Co. KG
Inventor： Stefan Rummele-Werner , Dietmar Fruhauf , Armin Wernet , Kaj Uppenkamp , Gerd Bechtel
CPC classification number: G06F1/08 , G01F23/266 , G06F1/0321 , G06F1/0328
Abstract: A signal generator for producing periodic signals for a measuring apparatus of automation technology. The signals have sequential, discrete signal frequencies, which lie within a predetermined frequency range. A control- and/or computing unit, a clock signal producer are provided, wherein the clock signal producer provides a constant sampling frequency, which is greater than the maximum discrete signal frequency in the predetermined frequency range. A memory unit is provided, in which for each of the discrete signal frequencies the amplitude values of the corresponding periodic signals are stored or storable as a function of the sampling frequency. The control- and/or computing unit reads out the stored or storable amplitude values of the discrete frequencies successively with the sampling frequency of the clock from the memory unit and produces the periodic signals, or forwards for producing. A static filter unit, is also provided with a limit frequency, which lies above the maximum signal frequency and which removes frequency fractions caused by the sampling.
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公开(公告)号：US10013018B2
公开(公告)日：2018-07-03
申请号：US15230484
申请日：2016-08-08
Applicant: Shenzhen Goodix Technology Co., Ltd.
Inventor： Guangyao Wang
CPC classification number: G06F1/0321 , G06F1/022 , G06F1/03 , G06F1/0328 , G06F1/035 , H03K3/012
Abstract: A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave according to the final interpolation data information of the sine wave.
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公开(公告)号：US20160321212A1
公开(公告)日：2016-11-03
申请号：US15205817
申请日：2016-07-08
Applicant: Syntropy Systems, LLC
Inventor： Christopher Pagnanelli
CPC classification number: G06F17/147 , G06F1/022 , G06F1/0328 , G06F1/04 , H03H17/04
Abstract: Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.
Abstract translation: 尤其提供了用于产生离散时间正弦曲线序列的系统，装置方法和技术。 一种这样的装置包括多个并行处理分支，其中每个并行处理分支以子采样速率运行，并利用递归滤波器产生代表由装置输出的完整信号的不同子采样相位的子速率采样 。
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公开(公告)号：US20160161975A1
公开(公告)日：2016-06-09
申请号：US15006088
申请日：2016-01-25
Applicant: Pentomics, Inc.
Inventor： Alan N. WILLSON, JR. , Tianyu HU , Yunfan LIU
Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to he responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.
Abstract translation: 提供了具有多个子相位累加器的分相相位累加器的系统和方法。 每个子相位累加器接收频率控制字的一部分。 第一子相位累加器包括第一寄存器，其余子相位累加器包括寄存器和溢出寄存器。 在每个离散时间点，第一子相位累加器被配置为响应于该离散时间点处的频率控制字的第一部分以及在紧接的先前离散时间点处的第一子相位累加器值，以及 剩余子相累加器中的每一个被配置为响应于在该离散时间点的频率控制字的对应部分的值以及在紧接的先前离散时间点处的相同的第二子相位累加器值。
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