公开(公告)号：US5781133A

公开(公告)日：1998-07-14

申请号：US792194

申请日：1997-01-30

申请人： Kinhing Paul Tsang

发明人： Kinhing Paul Tsang

IPC分类号： H03M7/14 ,  G06T9/00 ,  G11B20/14 ,  H03M5/14 ,  H03M7/46

CPC分类号： G11B20/1426 ,  G06T9/005 ,  H03M5/145 ,  G11B2020/1446

摘要： An apparatus encodes data blocks into code blocks, each code block containing more symbols than its respective data block. The apparatus includes a data block latch for receiving individual data blocks and for dividing each data block into two sub-blocks. An encoder receives one of the data sub-blocks and encodes the first data sub-block as a code sub-block. An interleaver, coupled to the encoder and the data block latch, combines the code sub-block with the second data sub-block to produce a code block, such that when the code blocks are concatenated with each other to produce a string of code symbols no more than five consecutive occurrences of a particular code symbol are present in the string of code symbols.

摘要翻译： 一种装置将数据块编码为码块，每个码块包含比其相应数据块更多的码元。 该装置包括用于接收各个数据块并将每个数据块划分成两个子块的数据块锁存器。 编码器接收数据子块中的一个，并将第一数据子块编码为码子块。 耦合到编码器和数据块锁存器的交织器将代码子块与第二数据子块组合以产生代码块，使得当代码块彼此级联以产生一串代码符号 代码符号串中不存在多于五个连续出现的特定代码符号。

公开(公告)号：US5757822A

公开(公告)日：1998-05-26

申请号：US518945

申请日：1995-08-24

申请人： Kevin D. Fisher ,  Pablo A. Ziperovich

发明人： Kevin D. Fisher ,  Pablo A. Ziperovich

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M7/14 ,  H03M13/27 ,  H03M13/00 ,  H03M5/00 ,  H03M7/00

CPC分类号： G11B20/1866 ,  G11B20/10009 ,  G11B20/1426 ,  H03M13/27 ,  G11B2020/1434 ,  G11B2020/1446

摘要： A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of: shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs, encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, and interleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.

摘要翻译： 调制方法根据以下步骤生成用于通过数据传送通道传送具有三路ECC交错的用户数字数据字节的速率16/17（d = 0，G = 7 / I = 11）调制码：洗牌 用户数据字节，以便以预定方式重新排列字节顺序并输出AiBi字节对，根据预定速率8/9调制码对AiBi字节对的Ai字节的8位进行编码，以产生9 代码比特a0-a8，并且根据预定的按位交织模式，将每个Ai字节的九个码比特a0-a8与每个Bi字节的八个未编码比特交织，以生成速率16/17调制码。 还描述了调制方法的优选代码和电路。

公开(公告)号：US07873894B2

公开(公告)日：2011-01-18

申请号：US11690635

申请日：2007-03-23

申请人： Evangelos S. Eleftheriou ,  Robert A. Hutchins ,  Thomas Mittelholzer ,  Paul J. Seger

发明人： Evangelos S. Eleftheriou ,  Robert A. Hutchins ,  Thomas Mittelholzer ,  Paul J. Seger

IPC分类号： H03M13/00

CPC分类号： G11B20/1426 ,  G11B20/1833 ,  G11B2020/1446 ,  G11B2220/2516 ,  G11B2220/90

摘要： Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

摘要翻译： 提供方法和计算机程序产品以对用于记录到介质上的数据进行编码，从而施加来自级联代码或产品代码的调制和线性约束。 生成第一组未编码的用户数据。 每行被调制编码以执行第一调制约束; 该阵列被变换成第二阵列，该第二阵列被转换成具有与调制数据交错的每列中的预定空位置的第三阵列。 对于第三阵列的至少一些空位置计算C2奇偶校验字节，并且生成第四阵列。 计算每行中的C1奇偶校验符号，生成第五个数组。 在第五阵列的每行中的每个C1奇偶校验符号上强制执行第二调制约束，产生第六阵列。 第六阵列的行与标题和同步字段组合，用于记录到记录介质上。

公开(公告)号：US20100177422A1

公开(公告)日：2010-07-15

申请号：US12351747

申请日：2009-01-09

申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

IPC分类号： G11B5/09 ,  G11B5/78

CPC分类号： G11B20/1833 ,  G11B20/1201 ,  G11B20/1866 ,  G11B2020/1287 ,  G11B2020/1289 ,  G11B2020/1446 ,  G11B2020/1836 ,  G11B2220/93 ,  H03M13/27 ,  H03M13/271

摘要： For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1−K1 C1-parity bytes are generated for each row and N2−K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.

摘要翻译： 为了将数据写入多轨磁带，接收到的数据集并被分割成未编码的子数据集，每个子​​集包括具有K2行和K1列的阵列。 对于每个未编码的子数据集，为每行生成N1-K1 C1-奇偶校验字节，并为每列生成N2-K2 C2-奇偶校验字节。 C1和C2奇偶校验字节分别附加到行和列的末端，分别形成编码的C1和C2码字。 每个数据集的所有C1码字都具有特定的码字头以形成多个部分码字对象（PCO）。 每个PCO根据标题内的信息被映射到逻辑数据轨道上。 在每个逻辑数据轨道上，相邻的PCO被合并以形成被调制编码并被映射到同步的CO中的CO。 然后将T同步的CO同时写入数据磁带，其中T是数据磁带上的并发活动磁道的数量。

公开(公告)号：US20080284624A1

公开(公告)日：2008-11-20

申请号：US11749711

申请日：2007-05-16

申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

IPC分类号： H03M7/00

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1446 ,  G11B2020/1473 ,  G11B2220/90 ,  G11B2220/956

摘要： An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) preceding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

摘要翻译： 未编码的m位数据输入序列被分成n位块和m-n位块。 n位的块被划分为第一组n + 1个编码比特，其中第一组的P1个子块中的至少一个满足G，M和I约束。 第一组n + 1个编码比特被映射到n + 1编码比特的第二组，其中第二组的P2个子块中的至少一个在1 /（1 + D 2）之后产生至少Q1个转换 ）。 第二组n + 1编码比特被分成P3编码子块，并且P3编码子块在（mn）/ s个未编码符号之间进行交织，以形成第（m + 1）比特的输出序列码字，然后存储在 数据存储介质。

公开(公告)号：US07057536B2

公开(公告)日：2006-06-06

申请号：US11031529

申请日：2005-01-10

申请人： Jun Lee ,  Joo-hyun Lee ,  Kyu-suk Lee ,  Jae-jin Lee

发明人： Jun Lee ,  Joo-hyun Lee ,  Kyu-suk Lee ,  Jae-jin Lee

IPC分类号： H03M7/00

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1434 ,  G11B2020/1446

摘要： Provided are a rate 13/15 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a predetermined rate-13/15 MTR code in which 13-bit data corresponds to 15-bit data; outputting input 13-bit data as a 15-bit codeword according to the rate-13/15 MTR code; checking whether codewords satisfy a predetermined constraint condition by connecting the 15-bit codeword and a subsequent 15-bit codeword; and converting specific bits of the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition. The rate-13/15 MTR (j=2, k=8) code includes: 8192 codewords obtained to prevent the number of consecutive transitions from becoming 3 at code boundaries in a modulation coding process. Data can be reliably reproduced with high write density, and a large amount of data can be stored in and reproduced from a magnetic recording information storage medium.

摘要翻译： 提供了一种速率13/15的MTR码编码/解码方法和装置。 编码方法包括：生成13比特数据对应于15比特数据的预定速率-13 / 15MTR码; 根据速率-13 / 15MTR码输出13位数据作为15位码字; 通过连接15位码字和随后的15位码字来检查码字是否满足预定约束条件; 以及如果所述码字违反所述约束条件并且如果所述码字不违反所述约束条件则不转换所述码字，则转换所述码字的特定比特。 速率-13 / 15MTR（j = 2，k = 8）码包括：8192个码字，用于防止在调制编码过程中连续转换的数目在码边界处变为3。 可以以高写入密度可靠地再现数据，并且可以将大量数据存储在磁记录信息存储介质中并从磁记录信息存储介质再现。

公开(公告)号：US07053801B2

公开(公告)日：2006-05-30

申请号：US10869843

申请日：2004-06-18

申请人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

发明人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B20/10009 ,  G11B20/1833 ,  G11B2020/1446 ,  H03M5/145 ,  H03M13/093

摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

摘要翻译： 一种装置具有转换电路，预编码器电路和选择电路。 转换电路转换用户数据b 1，b 2，b 3 3。 。 。 对于编码序列c 0，c 1，c 2，...， 。 。 c 。 选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。 。 。 使得预编码器电路的输出具有小于转换的最大数量q。 转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。 。 。 c 到序列c 1，c 2。 。 。 以及向序列c 1，c 2 2加上c 0的转换最小化电路。 。 。 c 。 该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。 。 。 c 。

公开(公告)号：US06985320B2

公开(公告)日：2006-01-10

申请号：US10037753

申请日：2002-01-02

申请人： Mario Blaum ,  Glen Alan Jaquette ,  Brian Harry Marcus ,  Constantin Michael Melas

发明人： Mario Blaum ,  Glen Alan Jaquette ,  Brian Harry Marcus ,  Constantin Michael Melas

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B5/00813 ,  G11B5/09 ,  G11B20/1426 ,  G11B2020/1434 ,  G11B2020/1446

摘要： Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

公开(公告)号：US06812867B2

公开(公告)日：2004-11-02

申请号：US10455696

申请日：2003-06-05

申请人： Roy D Cideciyan ,  Ajay Dholakia ,  Evangelos S Eleftheriou ,  Richard L Galbraith ,  Thomas Mittelholzer ,  Travis R Oenning ,  David J Stanek

发明人： Roy D Cideciyan ,  Ajay Dholakia ,  Evangelos S Eleftheriou ,  Richard L Galbraith ,  Thomas Mittelholzer ,  Travis R Oenning ,  David J Stanek

IPC分类号： H03M700

CPC分类号： H03M7/46 ,  G11B20/1426 ,  G11B2020/1446 ,  H03M5/145

摘要： Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.

摘要翻译： 描述了一种具有有限状态机的调制编码器，用于将输入比特转换成输出比特，其中交替输出比特的数量被限制为j + 1，其中j是输出比特中的预定义的最大转移数， 类似的输出位被限制为k + 1，其中k是输出位中的非转换的预定最大数量。 调制编码器可以用于将输入比特流转换成输出比特流的编码装置。 这种装置可以包括用于将输入比特流分成第一组比特和第二组比特的分区逻辑。 多个上述调制编码器可以连接到用于将第一组位转换为编码输出位的分割逻辑。 组合逻辑可以连接到或每个调制编码器和用于组合编码的输出位和第二组位的分区逻辑以产生输出比特流。 还描述了对位调制解码器和解码装置。

公开(公告)号：US06798593B2

公开(公告)日：2004-09-28

申请号：US09814548

申请日：2001-03-22

申请人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

发明人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

IPC分类号： G11B509

CPC分类号： H03M13/2957 ,  G11B20/10194 ,  G11B20/1426 ,  G11B20/1833 ,  G11B20/1866 ,  G11B2020/1434 ,  G11B2020/1446 ,  H03M13/6325

摘要： A magnetic recording and/or reproducing apparatus which achieves high performance encoding and high efficiency decoding to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction coding input data and an interleaver 52 for scrambling the sequence of data supplied from the error correction coder 51. The magnetic recording and/or reproducing apparatus 50 also includes, in its reproducing system, s modulation and error correction turbo decoder 64 provided with a deinterleaver for scrambling and re-arraying the sequence of the input data such as to restore the sequence of input data re-arrayed by the interleaver 52 to an original bit sequence, an error correction soft decoder for decoding data supplied from the deinterleaver and with a second interleaver for scrambling and re-arraying the sequence of data given as a difference between data output from the error correction soft decoder and data output from the deinterleaver.

摘要翻译： 一种实现高性能编码和高效率解码以降低解码错误率的磁记录和/或再现装置。 磁记录和/或再现装置50在其记录系统中包括用于纠错编码输入数据的纠错编码器51和用于对从纠错编码器51提供的数据序列进行加扰的交织器52.磁记录和/ 或再现装置50在其再现系统中还包括设置有去交织器的调制和纠错turbo解码器64，用于对输入数据的序列进行加扰和重新排列，以便恢复由所述解交织器重新排列的输入数据的序列 交织器52到原始比特序列，纠错软解码器，用于对从解交织器提供的数据进行解码，以及用于第二交织器，用于加扰和重新排列作为从纠错软解码器输出的数据与数据之间的差异的数据序列 从解交织器输出。