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70 条记录 (耗时 0.049 秒)

    Error propagation limiting encoder/decoder for multilevel decision feedback equalization
    4.
    发明授权
    Error propagation limiting encoder/decoder for multilevel decision feedback equalization 失效
    用于多级判决反馈均衡的误差传播限制编码器/解码器

    公开(公告)号：US6141783A

    公开(公告)日：2000-10-31

    申请号：US58509

    申请日：1998-04-10

    申请人： Jonathan James Ashley ,  Mario Blaum ,  Brian Harry Marcus ,  Constantin Michael Melas

    发明人： Jonathan James Ashley ,  Mario Blaum ,  Brian Harry Marcus ,  Constantin Michael Melas

    IPC分类号： G11B20/18 ,  H03M13/00 ,  H04L1/00 ,  H04L25/03 ,  G06F11/00 ,  G06F11/30

    CPC分类号： H04L1/0041 ,  G11B20/18 ,  H03M13/00 ,  H04L1/0045 ,  H04L25/03057

    摘要： The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

    摘要翻译： 本发明是一种编码器和解码器，其消除了许多抽头集合的所有无限传播的误差序列。 编码器包括可操作以接收未编码数据信号的输入电路和耦合到输入电路的编码电路，其可操作以使用代码消除无编传播的错误序列的编码数据信号，当编码数据信号由判定恢复时 反馈均衡器数据恢复通道。 解码器包括可操作以接收编码数据信号的输入电路和耦合到输入电路的解码表，该编码数据信号和解码表用于当编码数据信号被决定恢复时，使用消除无限传播的错误序列的代码产生解码数据信号 反馈均衡器数据恢复通道。

    Data storage to enhance timing recovery in high density magnetic recording
    5.
    发明授权
    Data storage to enhance timing recovery in high density magnetic recording 失效
    数据存储可增强高密度磁记录中的定时恢复

    公开(公告)号：US06429986B1

    公开(公告)日：2002-08-06

    申请号：US08816648

    申请日：1997-03-13

    申请人： Mario Blaum ,  Constantin Michael Melas

    发明人： Mario Blaum ,  Constantin Michael Melas

    IPC分类号： G11B509

    CPC分类号： G11B20/1426 ,  G11B5/09

    摘要： A timing recovery system encodes data while impressing recognizable patterns thereon, enabling precise timing during subsequent readback operations. An uncoded binary sequence is encoded using an m/n rate block coded sequence, incorporating a unique predetermined binary bit pattern that occurs with a selected level of frequency. The encoded sequence is stored on the recording medium as a series of flux transitions. To read back the stored data, a read head measures the flux transitions stored on the medium and generates a representative analog waveform. A sampler samples the waveform in accordance with a timing scheme provided by a timing circuit. The timing circuit adjusts the timing of the samples to ensure that the analog waveform is sampled at appropriate times to yield the most accurate results. The timing circuit evaluates two consecutive samples to identify samples associated with features of the analog readback waveform that corresponds to the predetermined bit patterns. Identified samples are then compared to determine whether timing of samples should be advanced, retarded, or retained with respect to the analog waveform. After a detector translates samples into an enclosed binary bit stream, a decoder decodes the detector's binary bit stream by revising the original encoding process, recreating the original encoded binary sequence.

    摘要翻译： 定时恢复系统对数据进行编码，同时在其上印刷可识别的图案，从而在随后的回读操作期间实现精确的定时。 使用m / n速率块编码序列对未编码的二进制序列进行编码，结合以所选频率出现的唯一预定二进制位模式。 编码序列作为一系列通量转换存储在记录介质上。 为了回读存储的数据，读取头测量存储在介质上的通量转换并产生代表性的模拟波形。 采样器根据定时电路提供的定时方案采样波形。 定时电路调整采样的时序，以确保模拟波形在适当的时间采样，以获得最准确的结果。 定时电路评估两个连续采样，以识别与对应于预定位模式的模拟回读波形的特征相关联的样本。 然后比较识别的样品，以确定样品的时序是否相对于模拟波形进行提前，延迟或保留。 在检测器将样本转换为封闭的二进制比特流之后，解码器通过修改原始编码过程来解码检测器的二进制比特流，重新创建原始编码的二进制序列。

    Defect tolerant binary synchronization mark
    6.
    发明授权
    Defect tolerant binary synchronization mark 失效
    缺陷容错二进制同步标记

    公开(公告)号：US5999110A

    公开(公告)日：1999-12-07

    申请号：US24422

    申请日：1998-02-17

    申请人： Mario Blaum ,  Steven Robert Hetzler ,  Glen Alan Jaquette ,  William John Kabelac

    发明人： Mario Blaum ,  Steven Robert Hetzler ,  Glen Alan Jaquette ,  William John Kabelac

    IPC分类号： G11B20/14 ,  G11B20/12 ,  G11B20/18 ,  H03M7/00 ,  H03M13/00

    CPC分类号： G11B20/1403 ,  G11B2020/1476 ,  G11B2220/90

    摘要： Disclosed is an error tolerant binary encoded synchronization mark concatenated with a known pattern, such as a VFO pattern, comprising an encoded pattern of a fixed plurality of bits, the encoded synchronization pattern being at maximum Hamming distance from the concatenated known pattern for the number of bits in the fixed plurality of bits. The error tolerant synchronization mark may also be concatenated with the VFO pattern seen in reverse, and the synchronization pattern additionally is at maximum Hamming distance from the concatenated known VFO pattern seen in reverse.

    摘要翻译： 公开了一种容错二进制编码同步标记，其与已知模式连接，诸如VFO模式，包括固定多个位的编码模式，编码同步模式距离级联已知模式的最大汉明距离为 固定多个比特中的比特。 误差同步标记也可以与反向看到的VFO模式相连，并且同步模式另外与从反向看到的级联的已知VFO模式相距最大的汉明距离。

    Nested Multiple Erasure Correcting Codes for Storage Arrays
    7.
    发明申请
    Nested Multiple Erasure Correcting Codes for Storage Arrays 有权
    存储阵列的嵌套多重擦除校正码

    公开(公告)号：US20120331367A1

    公开(公告)日：2012-12-27

    申请号：US13563123

    申请日：2012-07-31

    申请人： Mario Blaum ,  James L. Hafner ,  Steven R. Hetzler

    发明人： Mario Blaum ,  James L. Hafner ,  Steven R. Hetzler

    IPC分类号： H03M13/29 ,  G06F11/10

    CPC分类号： G06F11/108 ,  G06F2211/1045 ,  G06F2211/1057 ,  G06F2211/1059

    摘要： Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r-1 rows, up to tr-2 erasures in any one of the remaining r-2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.

    摘要翻译： 本发明的实施例涉及将数据存储在存储阵列中。 本发明的一个方面包括接收写入数据。 写入数据被排列成r行和n列的页面，每个页面包括多个扇区。 使用页面上的多个水平和垂直擦除校正码对写入数据进行编码。 该编码允许在r行中的任何一行中从最多到三次的恢复进行恢复，直到剩余的r-1行中的任何一行中的tr-1次擦除，直到剩下的r-2行中的任一个中的tr-2擦除 ，等等，使得编码允许在最后剩余的行中从高达t1个删除恢复。 从编码输出编码的写入数据。 编码的写入数据被写入存储阵列中的n个存储设备上的写入条带。

    Techniques for identifying servo sectors in storage devices
    8.
    发明授权
    Techniques for identifying servo sectors in storage devices 有权
    用于识别存储设备中的伺服扇区的技术

    公开(公告)号：US07869152B2

    公开(公告)日：2011-01-11

    申请号：US11677854

    申请日：2007-02-22

    申请人： Mario Blaum ,  Mantle Yu ,  Bruce Wilson

    发明人： Mario Blaum ,  Mantle Yu ,  Bruce Wilson

    IPC分类号： G11B5/09

    CPC分类号： G11B5/59688 ,  G11B20/1217 ,  G11B2020/1281 ,  G11B2220/2516

    摘要： Techniques are provided for identifying the servo sectors in a track on a data storage device. A data storage device identifies the servo sectors in a track by reading distributed index bits from multiple servo sectors in a track. The data storage device analyzes only one index bit from each servo sector to identify the index of a track. In some embodiments, the index of a track can be identified after examining the index bits stored in a particular number of consecutive servo sectors, even in the presence of errors. The index bits in each track can have an error tolerance with a minimum Hamming distance greater than one. In other embodiments, a data storage device compares a sliding window of the index bits read from the servo sectors to all possible N-bit vectors that exist within a pattern of the index bits stored on a track.

    摘要翻译： 提供了用于识别数据存储设备上的轨道中的伺服扇区的技术。 数据存储装置通过从轨道中的多个伺服扇区读取分布式索引位来识别轨道中的伺服扇区。 数据存储设备仅分析来自每个伺服扇区的一个索引位以识别轨道的索引。 在一些实施例中，即使存在错误，也可以在检查存储在特定数量的连续伺服扇区中的索引位之后识别轨道的索引。 每个轨道中的索引位可以具有大于1的最小汉明距离的误差容差。 在其他实施例中，数据存储装置将从伺服扇区读取的索引位的滑动窗口与存储在轨道上的索引位的模式中存在的所有可能的N位向量进行比较。

    Systems Using Low Density Parity Check Codes For Correcting Errors
    9.
    发明申请
    Systems Using Low Density Parity Check Codes For Correcting Errors 有权
    使用低密度奇偶校验码纠正错误的系统

    公开(公告)号：US20090235142A1

    公开(公告)日：2009-09-17

    申请号：US12046108

    申请日：2008-03-11

    申请人： Richard Leo Galbraith ,  Bruce Alexander Wilson ,  Travis Roger Oenning ,  Mario Blaum ,  Ksenija Lakovic ,  Ivana Djurdjevic

    发明人： Richard Leo Galbraith ,  Bruce Alexander Wilson ,  Travis Roger Oenning ,  Mario Blaum ,  Ksenija Lakovic ,  Ivana Djurdjevic

    IPC分类号： H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/1111 ,  G11B20/18

    摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.

    摘要翻译： 系统校正位流中的错误。 该系统包括编码器和解码器。 编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。 解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。 奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。 低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。 编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。