-
公开(公告)号：US06985320B2
公开(公告)日：2006-01-10
申请号：US10037753
申请日：2002-01-02
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B5/00813 , G11B5/09 , G11B20/1426 , G11B2020/1434 , G11B2020/1446
摘要： Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.
-
公开(公告)号：US07116736B2
公开(公告)日：2006-10-03
申请号：US10038163
申请日：2002-01-02
CPC分类号： G11B20/1426 , G11B27/3027 , G11B2020/1446
摘要： Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is generated into at least one point in the data stream. An encoded data stream is formed by concatenating the synchronization mark with the received binary data. During decoding, the synchronization mark is detected based on error propagation occurring adjacent to the at least one isolated peak of the synchronization mark.
-
3.发明授权Adjusting a read detection equalizer filter of a magnetic tape drive employing a recording format required control pattern 有权调整采用记录格式所需控制模式的磁带驱动器的读取检测均衡器滤波器公开(公告)号：US06765741B2
公开(公告)日：2004-07-20
申请号：US10302885
申请日：2002-11-25
IPC分类号： G11B5035
CPC分类号： G11B5/035
摘要： Adjustment of a read detection equalizer filter of a magnetic tape drive is conducted utilizing a required control pattern signal which comprises a required portion of a normal recording format of the magnetic tape. An example comprises a data set separator signal. The sensed required control pattern signal is processed with respect to a target reference pattern signal to adapt the read detection equalizer filter to the target reference pattern signal.
摘要翻译： 使用包括磁带的正常记录格式的所需部分的所需控制模式信号来进行磁带驱动器的读检测均衡器滤波器的调整。 示例包括数据集分离器信号。 感测到的所需控制模式信号相对于目标参考模式信号被处理，以使读取的检测均衡器滤波器适应于目标参考模式信号。
-
4.发明授权Error propagation limiting encoder/decoder for multilevel decision feedback equalization 失效用于多级判决反馈均衡的误差传播限制编码器/解码器
公开(公告)号：US6141783A
公开(公告)日：2000-10-31
申请号：US58509
申请日：1998-04-10
CPC分类号： H04L1/0041 , G11B20/18 , H03M13/00 , H04L1/0045 , H04L25/03057
摘要： The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.
摘要翻译： 本发明是一种编码器和解码器，其消除了许多抽头集合的所有无限传播的误差序列。 编码器包括可操作以接收未编码数据信号的输入电路和耦合到输入电路的编码电路，其可操作以使用代码消除无编传播的错误序列的编码数据信号，当编码数据信号由判定恢复时 反馈均衡器数据恢复通道。 解码器包括可操作以接收编码数据信号的输入电路和耦合到输入电路的解码表，该编码数据信号和解码表用于当编码数据信号被决定恢复时，使用消除无限传播的错误序列的代码产生解码数据信号 反馈均衡器数据恢复通道。
-
公开(公告)号：US07639444B2
公开(公告)日：2009-12-29
申请号：US10737563
申请日：2003-12-15
CPC分类号： G11B20/10009
摘要： Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values.
摘要翻译： 公开了一种更新读取检测通道的技术。 在具有一个或多个可编程寄存器的读取检测通道中处理信号。 当信号继续由读取检测通道处理时，用信道辅助处理器确定是否动态地替换一个或多个可编程寄存器的值。 当确定要替换一个或多个可编程寄存器的值时，信道辅助处理器确定一个或多个可编程寄存器的值，并用所确定的值替换一个或多个可编程寄存器的现有值。
-
6.发明授权公开(公告)号：US06429986B1
公开(公告)日：2002-08-06
申请号：US08816648
申请日：1997-03-13
IPC分类号： G11B509
CPC分类号： G11B20/1426 , G11B5/09
摘要： A timing recovery system encodes data while impressing recognizable patterns thereon, enabling precise timing during subsequent readback operations. An uncoded binary sequence is encoded using an m/n rate block coded sequence, incorporating a unique predetermined binary bit pattern that occurs with a selected level of frequency. The encoded sequence is stored on the recording medium as a series of flux transitions. To read back the stored data, a read head measures the flux transitions stored on the medium and generates a representative analog waveform. A sampler samples the waveform in accordance with a timing scheme provided by a timing circuit. The timing circuit adjusts the timing of the samples to ensure that the analog waveform is sampled at appropriate times to yield the most accurate results. The timing circuit evaluates two consecutive samples to identify samples associated with features of the analog readback waveform that corresponds to the predetermined bit patterns. Identified samples are then compared to determine whether timing of samples should be advanced, retarded, or retained with respect to the analog waveform. After a detector translates samples into an enclosed binary bit stream, a decoder decodes the detector's binary bit stream by revising the original encoding process, recreating the original encoded binary sequence.
摘要翻译： 定时恢复系统对数据进行编码，同时在其上印刷可识别的图案，从而在随后的回读操作期间实现精确的定时。 使用m / n速率块编码序列对未编码的二进制序列进行编码，结合以所选频率出现的唯一预定二进制位模式。 编码序列作为一系列通量转换存储在记录介质上。 为了回读存储的数据，读取头测量存储在介质上的通量转换并产生代表性的模拟波形。 采样器根据定时电路提供的定时方案采样波形。 定时电路调整采样的时序，以确保模拟波形在适当的时间采样，以获得最准确的结果。 定时电路评估两个连续采样，以识别与对应于预定位模式的模拟回读波形的特征相关联的样本。 然后比较识别的样品，以确定样品的时序是否相对于模拟波形进行提前，延迟或保留。 在检测器将样本转换为封闭的二进制比特流之后，解码器通过修改原始编码过程来解码检测器的二进制比特流，重新创建原始编码的二进制序列。
-
公开(公告)号：US5946354A
公开(公告)日：1999-08-31
申请号：US730862
申请日：1996-10-18
IPC分类号： H04K1/10
摘要： A hard disk drive read circuit for d=1 run length limited (RLL) encoded data which processes multiple consecutive data samples in parallel. The circuit of the present invention receives an analog signal from the read head of the hard disk drive. The circuit comprises a plurality of digital detection channels, coupled to the analog signal, each channel outputting an alternate bit of digital data represented by the analog signal. A timing circuit, coupled to the plurality of digital detection channels, generates a plurality of timing signals controlling the plurality of digital detection channels. The timing circuit derives timing information from one of the digital detection channels. The d=1 RLL code is modified so that there are at most nine consecutive 0's in the digital data output by the digital detection channel from which the timing circuit derives the timing information. An encoder generates the encoded digital data to be recorded on the hard disk drive.
摘要翻译： 用于d = 1游程长度限制（RLL）编码数据的硬盘驱动器读取电路，并行处理多个连续的数据样本。 本发明的电路从硬盘驱动器的读取头接收模拟信号。 电路包括耦合到模拟信号的多个数字检测通道，每个通道输出由模拟信号表示的数字数据的交替位。 耦合到多个数字检测通道的定时电路产生控制多个数字检测通道的多个定时信号。 定时电路从数字检测通道之一获得定时信息。 修改d = 1 RLL码，使数字检测通道输出的数字数据中至少有九个连续的0，定时电路从该数字检测通道得到定时信息。 编码器生成要记录在硬盘驱动器上的编码数字数据。
-
8.发明授权Magnetic recording channel utilizing control fields for timing recovery, equalization, amplitude and amplitude asymmetry 有权磁记录通道利用控制场进行定时恢复，均衡，幅度和幅度不对称公开(公告)号：US07102839B2
公开(公告)日：2006-09-05
申请号：US10699132
申请日：2003-10-31
IPC分类号： G11B5/09
CPC分类号： G11B20/1403 , G11B5/012 , G11B5/035 , G11B5/09 , G11B20/10009 , G11B20/10481 , G11B2005/001 , G11B2005/0016 , G11B2005/0018
摘要： Channel parameters for a magnetic readback channel are optimized by detecting a readback signal that is recorded on a magnetic medium. The readback signal contains a plurality of predetermined-length control fields. Each control field is arranged between two user data fields and contains at least one transition. At least one selected readback parameter, such as a frequency of a readback channel system clock, a gain of the readback channel, a equalization response of the readback signal, and/or an amplitude asymmetry of the readback channel, is optimized based on information contained in at least one control field.
摘要翻译： 通过检测记录在磁性介质上的回读信号来优化磁回读通道的通道参数。 回读信号包含多个预定长度的控制字段。 每个控制字段被布置在两个用户数据字段之间并且包含至少一个转换。 基于所包含的信息来优化至少一个选择的回读参数，例如回读通道系统时钟的频率，回读通道的增益，回读信号的均衡响应和/或回读通道的幅度不对称性 在至少一个控制领域。
-
公开(公告)号：US06678105B2
公开(公告)日：2004-01-13
申请号：US09858907
申请日：2001-05-17
IPC分类号： G11B509
CPC分类号： G11B20/10046 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10055
摘要： A decoding circuit has a nonlinear equalizer which employs a signal conditioning algorithm for conditioning a partial response sampled signal to eliminate intersymbol interference. The inventive decoding circuit has an analog-to-digital converter for sampling an analog signal, a linear equalizer for adjusting the amplitude and phase relations of the sampled signal, a nonlinear equalizer for conditioning the sampled signal and outputting a partial response sampled signal having two nonzero samples, and a partial response maximum likelihood detector, for detecting the partial response sampled signal having two nonzero samples.
摘要翻译： 解码电路具有非线性均衡器，其采用信号调节算法来调节部分响应采样信号以消除符号间干扰。 本发明的解码电路具有用于对模拟信号进行采样的模拟 - 数字转换器，用于调整采样信号的幅度和相位关系的线性均衡器，用于调节采样信号的非线性均衡器，并输出具有两个 非零样本和部分响应最大似然检测器，用于检测具有两个非零样本的部分响应采样信号。
-
10.发明授权Asynchronous low sampling rate read channel using combination midpoint and linear interpolation 失效使用组合中点和线性插值的异步低采样率读通道
公开(公告)号：US06084924A
公开(公告)日：2000-07-04
申请号：US42121
申请日：1998-03-13
CPC分类号： G11B20/1426 , G11B5/09 , G11B20/10009
摘要： A method and apparatus for the recovery of information via asynchronous signal sampling of coded analog waveforms by double interpolating values into the train of asynchronously sampled signals prior to the train being applied to a synchronous detector. The double interpolation includes averaging successive sample signals and midpoint interpolating them between the sample, and then interpolating signals between the sample signals and midpoint signals closest to predicted synchronous points. This double interpolation facilitates low sampling rates while still effectuating accurate synchronous digital detection.
摘要翻译： 一种用于通过在将列车应用于同步检测器之前将数值双重内插到异步采样信号串中，通过异步信号采样编码模拟波形来恢复信息的方法和装置。 双插值包括平均连续采样信号和中点插值在样本之间，然后在采样信号和最接近预测同步点的中点信号之间内插信号。 这种双插补有助于低采样率，同时仍然实现精确的同步数字检测。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.024 秒)