公开(公告)号：US06603174B2

公开(公告)日：2003-08-05

申请号：US09197705

申请日：1998-11-23

Applicant: Shoichi Miyamoto ,  Yuuichi Hirano ,  Takashi Ipposhi

Inventor： Shoichi Miyamoto ,  Yuuichi Hirano ,  Takashi Ipposhi

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L21/28123 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/42384

Abstract: An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral portion of the SOI layer (3) is a silicon oxide film (6), the side surface (6H) of which is integrally joined to the side surface (8H) of the silicon oxide film (8). The thickness of the peripheral portion of the SOI layer (3) decreases as closer to the end portion (3H) of the SOI layer (3), while the thickness of the silicon oxide film (6) formed on the peripheral portion of the SOI layer (3) increases as closer to the end portion (3H). A gate oxide film (9) is formed on a predetermined region of the surface of the SOI layer (3), and joined to the silicon oxide film (6) at its end portion. A gate electrode (10) is then formed on the surface of the gate oxide film (9) and on a portion where the silicon oxide film (6) is integrally joined to the gate oxide film (9). In this manner, an SOI/MOSFET is obtained with no parasitic element formed at the end portion of the SOI layer.

Abstract translation: SOI衬底（30）包括掩埋氧化膜（2），形成在掩埋氧化膜的表面（2S）的第一区域（51）上的SOI层（3）和形成的氧化硅膜（8） 在表面（2S）的第二区域（52）上。 在SOI层（3）的周边部分上形成氧化硅膜（6），其氧化硅膜（6）的一侧与表面（8H）形成一体。 SOI层（3）的周边部的厚度比SOI层（3）的端部（3H）更靠近，而在SOI的外周部形成的氧化硅膜（6）的厚度 层（3）越靠近端部（3H）越大。 栅极氧化膜（9）形成在SOI层（3）的表面的规定区域上，并在其端部与氧化硅膜（6）接合。 然后，在栅极氧化膜（9）的表面和氧化硅膜（6）与栅氧化膜（9）整体接合的部分上形成栅电极（10）。 以这种方式，在SOI层的端部没有形成寄生元件的SOI / MOSFET得到。

公开(公告)号：US06573153B2

公开(公告)日：2003-06-03

申请号：US10073337

申请日：2002-02-13

Applicant: Shigenobu Maeda

Inventor： Shigenobu Maeda

IPC: H01L2176

CPC classification number: H01L21/76264 ,  H01L21/76281 ,  H01L21/84 ,  Y10S438/928

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

公开(公告)号：US20020192961A1

公开(公告)日：2002-12-19

申请号：US10211360

申请日：2002-08-05

Inventor： Motoki Kobayashi

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/02046 ,  H01L21/02052 ,  H01L21/32 ,  H01L21/76264 ,  H01L21/76281

Abstract: A method for forming an isolation region on a semiconductor substrate with a high yield, comprising partially covering the surface of a semiconductor substrate with an oxidation inhibitor film, depositing a material for side-wall parts on the oxidation inhibitor film and also on an exposed region of the surface, which is revealed through an opening of the oxidation inhibitor film, to form side-wall parts at the edge portions of the oxidation inhibitor film, then, removing by a plasma etching process the unnecessary portions of said side-wall material deposited on the oxidation inhibitor film and on the exposed region of the substrate and leaving intact the side-wall parts at the edge portions of the oxidation inhibitor film, and cleaning the exposed region on the surface of the semiconductor substrate, revealed through the opening of the oxidation inhibitor film, before subsequent heat treatment to generate a field oxide film.

公开(公告)号：US06472712B1

公开(公告)日：2002-10-29

申请号：US09357922

申请日：1999-07-21

Applicant: Toru Nakura ,  Kimio Ueda

Inventor： Toru Nakura ,  Kimio Ueda

IPC: H01L2976

CPC classification number: H01L21/76264 ,  H01L21/76281 ,  H01L27/1203

Abstract: A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Abstract translation: 提供了改善以抑制晶体管的漏电流的半导体器件。 栅电极设置在半导体衬底上。 在栅极长度方向Y上的栅电极的两侧，在半导体衬底的表面上设置一对p型源极/漏极层。在半导体衬底的表面上设置n型栅极宽度确定层， 在栅电极的宽度方向X上夹着源极/漏极层，这决定了栅电极的栅极宽度。 源极/漏极层和栅极宽度确定层通过PN结隔离。

公开(公告)号：US06465296B1

公开(公告)日：2002-10-15

申请号：US10167095

申请日：2002-06-10

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L218238

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract translation: 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

公开(公告)号：US20020119627A1

公开(公告)日：2002-08-29

申请号：US10133350

申请日：2002-04-29

Applicant: OKI ELECTRIC INDUSTRY CO., LTD

Inventor： Toshiyuki Nakamura

IPC: H01L021/336 ,  H01L021/76 ,  H01L027/12 ,  H01L029/00

CPC classification number: H01L29/66772 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66628 ,  H01L29/78618

Abstract: The present invention aims to provide a field effect transistor which inhibits an aggregation of silicon atoms attendant on heat treatment and has stable source/drain shapes. The field effect transistor according to the present invention is manufactured using a substrate on which a silicon layer, an buried oxide film (BOX film) and an SOI layer are stacked in order. The field effect transistor has an element isolation layer formed in the SOI layer and further includes visored portions provided so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer.

Abstract translation: 本发明旨在提供一种场效应晶体管，其抑制伴随热处理的硅原子的聚集并且具有稳定的源极/漏极形状。 根据本发明的场效应晶体管是使用其上依次层叠硅层，掩埋氧化膜（BOX膜）和SOI层的基板来制造的。 场效应晶体管具有形成在SOI层中的元件隔离层，并且还包括设置为覆盖由元件隔离层限定的激活层的主表面侧上的角部的遮挡部。

公开(公告)号：US20020048884A1

公开(公告)日：2002-04-25

申请号：US09510102

申请日：2000-02-22

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L021/00 ,  H01L021/336 ,  H01L021/84

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal which forms the semiconductor channel in the substrate. Contacts are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract translation: 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成直接或通过咸水接触区域垂直连接到暴露的源极/漏极接点的接触。

公开(公告)号：US20020045326A1

公开(公告)日：2002-04-18

申请号：US09791984

申请日：2001-02-23

Inventor： Yoko Sato ,  Akihiko Ebina

IPC: H01L021/00 ,  H01L021/84 ,  H01L021/331 ,  H01L021/8222 ,  H01L021/30 ,  H01L021/46 ,  H01L021/425

CPC classification number: H01L21/76264 ,  H01L21/76281 ,  H01L27/1203

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract translation: 某些实施例涉及制造抑制寄生器件形成的半导体器件的方法。 制造半导体器件的方法包括限定步骤和掺杂剂注入步骤。 定界步骤部分氧化设置在半导体衬底11上的单晶硅层，其间具有绝缘层，以形成由绝缘层16限定的多个隔离的单晶硅层段13a。在注入步骤中，掺杂剂 将离子18注入到单晶硅层段13a中以激活单晶硅层段13a。 在该注入步骤中，通过注入能量将掺杂剂注入到单晶硅层段13a中，所述注入能量被设定为使得掺杂剂浓度的最大值的位置位于每个单晶的底部边缘Ea和Eb 硅层段13a。

公开(公告)号：US06353254B1

公开(公告)日：2002-03-05

申请号：US09717304

申请日：2000-11-22

Applicant: Chang-Jae Lee ,  Jae-Il Ju

Inventor： Chang-Jae Lee ,  Jae-Il Ju

IPC: H01L2900

CPC classification number: H01L21/3081 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283

Abstract: The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.

Abstract translation: 本发明涉及半导体功率IC中的器件隔离结构和器件隔离方法。 根据本发明的器件隔离结构包括：包括高电压区域和低电压区域的半导体衬底; 与半导体衬底的高压器件区域重叠的沟槽和形成在高电压器件区域和低电压器件区域之间的界面区域; 第四绝缘膜，第五绝缘膜和顺序层叠在沟槽中的导电膜; 形成在包括沟槽的半导体衬底上的第一绝缘膜图案; 以及分别形成在所述沟槽上和所述半导体衬底的从所述第一绝缘膜图案露出的所述上表面的一部分上的场绝缘膜。 本发明具有制造成本和可靠性方面的几个优点，其中一些优点是通过在导电膜的空的空间中形成热氧化膜来实现的，氧空气通过氧化膜渗入其中，从而抑制在高压装置之间产生的击穿 高压。

公开(公告)号：US20020016025A1

公开(公告)日：2002-02-07

申请号：US09481385

申请日：2000-01-12

Inventor： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC: H01L021/00 ,  H01L021/84 ,  H01L021/76

CPC classification number: H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/0638 ,  H01L29/78609

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract translation: 形成侧壁氧化物层和侧壁绝缘层以覆盖SOI层的边缘部分。 在SOI层的边缘部附近形成沟道阻挡区域。 在沟道阻挡区域上形成突出的绝缘层。 栅电极从SOI层上的区域延伸到突出的绝缘层和侧壁绝缘层。 以这种方式，可以抑制在SOI层的边缘部分处的寄生MOS晶体管的阈值电压Vth的降低。