公开(公告)号：US20160233991A1

公开(公告)日：2016-08-11

申请号：US15019483

申请日：2016-02-09

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04L1/20 ,  H04L7/00 ,  H04L1/24 ,  H04L7/10

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

公开(公告)号：US09413497B2

公开(公告)日：2016-08-09

申请号：US14201559

申请日：2014-03-07

Applicant: JDSU Deutschland GMBH

Inventor： Reiner Schnizler ,  Paul Brooks

IPC: H04L1/24 ,  H04L25/06 ,  H04L1/20 ,  G06F7/58 ,  G01R31/28

CPC classification number: H04L1/241 ,  G01R31/2822 ,  G01R31/2839 ,  G06F7/58 ,  H04L1/20 ,  H04L1/244 ,  H04L25/064

Abstract: The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

Abstract translation: 本发明涉及一种用于测试数据链路的方法和设备。 通过数据链路传输一个或多个PRBS信号的单通道或多通道位错误测试器用用于存储针对每个检测到的错误事件的位错误信息的原始位错误缓冲器和错误模式分析器来增加。 识别最经常出现的车道内位错误模式，车道间字错误模式和位滑动模式，并分析其特性，以便提供指示检测到的位错误和位滑动的根本原因的信息。

公开(公告)号：US20150205653A1

公开(公告)日：2015-07-23

申请号：US14675064

申请日：2015-03-31

Applicant: Avago Technologies Limited

Inventor： Coralyn S. Gauvin ,  Gabriel L. Romero

IPC: G06F11/07

CPC classification number: G01R31/3193 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/08 ,  G06F11/277 ,  H04L1/241

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract translation: 测试模式使用游程长度限制行编码来编码以产生编码的数据块。 编码的数据块通过信道发送。 在发送数据中的最大长度运行之后的所接收的数据块中的多个比特与预期的多个比特进行比较。 基于预期的多个比特和接收的数据块中的多个比特之间的不匹配来分类一种比特错误。

公开(公告)号：US09021325B2

公开(公告)日：2015-04-28

申请号：US13761427

申请日：2013-02-07

Applicant: LSI Corporation

Inventor： Coralyn S. Gauvin ,  Gabriel L. Romero

IPC: G01R31/28 ,  G06F11/00 ,  G06F11/08 ,  G06F11/277 ,  G01R31/3193

CPC classification number: G01R31/3193 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/08 ,  G06F11/277 ,  H04L1/241

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract translation: 测试模式使用游程长度限制行编码来编码以产生编码的数据块。 编码的数据块通过信道发送。 在发送数据中的最大长度运行之后的所接收的数据块中的多个比特与预期的多个比特进行比较。 基于预期的多个比特和接收的数据块中的多个比特之间的不匹配来分类一种比特错误。

公开(公告)号：US08468397B2

公开(公告)日：2013-06-18

申请号：US12974336

申请日：2010-12-21

Applicant: Iwao Yamazaki

Inventor： Iwao Yamazaki

IPC: G06F11/00 ,  H04L1/24

CPC classification number: H04L1/241 ,  G06F11/2215 ,  G06F11/267

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract translation: 误差控制系统包括多个误差产生目标电路，多个伪误差产生装置，每个具有保持定向伪误差内容的伪误差内容保持寄存器，每个伪误差产生装置产生与伪伪对象相对应的伪误差 在要被写入多个错误产生目标电路之一的数据中的至少一个中保存在相应的伪错误内容保持寄存器中的错误内容以及在被指示生成时将从多个错误产生目标电路之一读取的数据 所述伪错误控制装置和伪错误控制装置，其指示所述多个伪错误生成装置生成与在所述多个伪错误中的每一个中提供的所述伪错误内容保持寄存器中的每一个中保持的各个伪错误内容相对应的伪错误 生成设备。

公开(公告)号：US20130142226A1

公开(公告)日：2013-06-06

申请号：US13648614

申请日：2012-10-10

Applicant: ALAXALA Networks Corporation

Inventor： Toru Sasaki ,  Junji Baba ,  Naohisa Koie

IPC: H04B1/38

CPC classification number: H04L25/0272 ,  H04L1/241

Abstract: A signal transmission system comprises: a first circuit; a second circuit; a transmission line configured to transmit data from the first circuit to the second circuit by using a differential signal; a monitor configured to monitor an interval of transmission of the data; and a compensator configured to correct a transmission loss of the differential signal in the interval monitored by the monitor.

Abstract translation: 信号传输系统包括：第一电路; 第二电路; 配置为通过使用差分信号将数据从第一电路传输到第二电路的传输线; 监视器，被配置为监视数据的传输间隔; 以及补偿器，被配置为校正由监视器监视的间隔中的差分信号的传输损耗。

公开(公告)号：US20110161747A1

公开(公告)日：2011-06-30

申请号：US12974336

申请日：2010-12-21

Applicant: Iwao YAMAZAKI

Inventor： Iwao YAMAZAKI

IPC: G06F11/00

CPC classification number: H04L1/241 ,  G06F11/2215 ,  G06F11/267

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract translation: 误差控制系统包括多个误差产生目标电路，多个伪误差产生装置，每个具有保持定向伪误差内容的伪误差内容保持寄存器，每个伪误差产生装置产生与伪伪对象相对应的伪误差 在要被写入多个错误产生目标电路之一的数据中的至少一个中保存在相应的伪错误内容保持寄存器中的错误内容以及在被指示生成时将从多个错误产生目标电路之一读取的数据 所述伪错误控制装置和伪错误控制装置，其指示所述多个伪错误生成装置生成与在所述多个伪错误中的每一个中提供的所述伪错误内容保持寄存器中的每一个中保持的各个伪错误内容相对应的伪错误 生成设备。

公开(公告)号：US07596175B2

公开(公告)日：2009-09-29

申请号：US12134691

申请日：2008-06-06

Applicant: Fred F. Chen

Inventor： Fred F. Chen

IPC: H03H7/30 ,  H04L27/00

CPC classification number: H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract translation: 描述了配备有判决反馈均衡（DFE）或使用历史数据以减少符号间干扰（ISI）的其他形式的反馈的边缘测试接收机的方法和电路。 在一个示例中，具有DFE的高速串行接收机将正确的接收数据（即，“预期数据”）注入到反馈路径中，而不管接收机是否产生正确的输出数据。 因此，在存在接收器错误的情况下，维持利润率，允许在系统边际测试中探查边界边界，而不会使边界限制崩溃。 一些接收器包括存储或生成裕量测试的预期数据的本地预期数据源。 其他实施例从应用于接收机输入端的测试数据导出预期数据。

公开(公告)号：US20060184707A1

公开(公告)日：2006-08-17

申请号：US11056066

申请日：2005-02-11

Applicant: Gregg Lesartre

Inventor： Gregg Lesartre

IPC: G06F13/36

CPC classification number: H04L1/241 ,  H04L43/50

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract translation: 采用串行化器和解串器的数据通信架构可以减少数据通信延迟。 在说明性实现中，数据通信架构通过通信链路传送数据。 该架构维护各种机制，以提升数据通信速度，避免通信链路停机。 这些机制执行包括但不限于生成处理调试信息，处理链路识别信息，跨通信链路注入错误并执行错误检测的功能。

公开(公告)号：US20060143549A1

公开(公告)日：2006-06-29

申请号：US11275313

申请日：2005-12-22

Applicant: Akira Yasumoto ,  Susuma Akada ,  Minoru Nishiyama

Inventor： Akira Yasumoto ,  Susuma Akada ,  Minoru Nishiyama

IPC: G06F11/00

CPC classification number: H04L1/244 ,  H04L1/203 ,  H04L1/241

Abstract: A bit error rate (BER) measuring apparatus is provided for measuring BER of an out-of-band tuner. The BER measuring apparatus generates a test signal for measuring the BER of the out-of-band tuner using a transport stream including a pseudo-random bit string (PRBS). In one embodiment, the BER measuring apparatus comprises a BER test signal generator that generates the test signal which includes a transport stream for transmission. The BER measuring apparatus also comprises a BER detector that detects the BER from a received test signal generated by the tuner in response to the test signal from the BER test signal generator. In one embodiment, the test signal generator comprises a PRBS generator that generates a first PRBS, and a transport stream framing circuit that frames the first PRBS into a transport stream form to generate the transport stream for transmission.

Abstract translation: 提供误码率（BER）测量装置用于测量带外调谐器的BER。 BER测量装置使用包括伪随机位串（PRBS）的传输流生成用于测量带外调谐器的BER的测试信号。 在一个实施例中，BER测量装置包括BER测试信号发生器，其产生包括用于传输的传输流的测试信号。 BER测量装置还包括BER检测器，其响应于来自BER测试信号发生器的测试信号，从接收到的由调谐器产生的测试信号检测BER。 在一个实施例中，测试信号发生器包括产生第一PRBS的PRBS发生器以及传输流成帧电路，其将第一PRBS成帧为传输流形式以产生用于传输的传输流。