公开(公告)号：US20040036894A1

公开(公告)日：2004-02-26

申请号：US10364518

申请日：2003-02-12

Applicant: CANON KABUSHIKI KAISHA

Inventor： Masahiko Murata

IPC: H04N001/387 ,  G06F003/12 ,  G06T003/60 ,  G06F003/05

CPC classification number: G06K15/02 ,  G06K15/1851

Abstract: Band rendering processing time in the case where the raster scanning direction of inputted output information and that of a print mechanism are different can be remarkably reduced, and rendering processing efficiency of each page is improved. To expect the further improvement of throughput, a display list to render objects into a band memory is formed on the basis of the inputted output information. A bit map image is rendered into the band memory in accordance with the display list. If it is determined that the raster scanning direction of the inputted output information and that of the print mechanism are different, a rotating process is executed to the bit map image rendered in a rendering step so as to be matched with the raster scanning direction of the print mechanism and the rotated data is transferred to the print mechanism.

Abstract translation: 在输入的输出信息的光栅扫描方向和打印机构的光栅扫描方向不同的情况下的带渲染处理时间可以显着地减少，并且提高了每页的渲染处理效率。 为了期望进一步提高吞吐量，基于输入的输出信息形成用于将对象呈现到带存储器中的显示列表。 根据显示列表将位图图像呈现到带存储器中。 如果确定输入的输出信息的光栅扫描方向和打印机构的光栅扫描方向不同，则对在渲染步骤中呈现的位图图像执行旋转处理，以便与 打印机构和旋转的数据被传送到打印机构。

公开(公告)号：US20030236932A1

公开(公告)日：2003-12-25

申请号：US10377673

申请日：2003-03-04

Applicant: SEIKO EPSON CORPORATION

Inventor： Nobuyuki Saito ,  Shun Oshita ,  Yoshiyuki Kamihara ,  Kuniaki Matsuda

IPC: G06F005/00 ,  G06F003/06 ,  G06F003/05 ,  G06F003/023 ,  G06F003/02 ,  G06F003/00

CPC classification number: G06F13/4286

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract translation: 当已经设置了第一模式（具有SOF模式）时，在帧周期传送SOF分组时执行数据传送，并且当已经设置了第二模式（非SOF模式）并且还非非周期（大量）传送 正在执行，SOF分组的周期性传输被禁用并且非周期性数据被传送。 如果没有要传送的非周期性数据，即使已经设置了第二模式，也在帧周期中传送SOF数据包。 在使用USB移动（OTG）的主机操作期间，管道区域被分配给分组缓冲器，并且在周期性地传送SOF分组被禁用时，非周期性数据被自动传送到端点或从端点传送。 当管道区域的所有自动传送指令信号都不活动时，即使设置了第二模式，也会周期性地传送SOF数据包。

公开(公告)号：US20030196009A1

公开(公告)日：2003-10-16

申请号：US10121564

申请日：2002-04-11

Applicant: International Business Machines Corporation

Inventor： Craig Fellenstein ,  Carl Phillip Gusler ,  Rick Allen Hamilton II ,  Timothy Moffett Waters

IPC: G06F003/00 ,  G06F003/02 ,  G06F003/023 ,  G06F003/05 ,  G06F003/06 ,  G06F005/00

CPC classification number: G06F3/0601 ,  G06F5/065 ,  G06F2003/0691 ,  G06F2003/0697

Abstract: A method and system are provided in which broadcast signals are received and converted into data streams for processing. A user is enabled to select preferred broadcast stations for monitoring and signals from the selected stations are converted into digital data streams which are input to first-in first-out (FIFO) memory units to enable a local storage of a segment of predetermined duration of broadcast signals on different FIFO tracks in a user receiving device. The FIFO is dynamically allocated for the selected stations and as each FIFO memory for each selected station becomes full, old information or content is moved out of memory as new information or content is applied to the FIFO. The receiving device includes means for enabling a user to move forward or backward within the stored segment. Partitions or markers are provided to separate broadcast content items, such as sequentially played songs within the stored segment, to enable incremental movement to selected positions within the stored segment. Sections of stored segments which are selected for user processing are copied to separate memory locations for access to avoid interference with the continuing FIFO storage of received broadcast signals.

Abstract translation: 提供一种方法和系统，其中广播信号被接收并转换成用于处理的数据流。 用户能够选择用于监视的优选广播站，并且来自所选择的站的信号被转换成数字数据流，其被输入到先进先出（FIFO）存储器单元，以使得能够本地存储预定持续时间的段 在用户接收设备中的不同FIFO轨道上的广播信号。 为所选择的站动态地分配FIFO，并且当新的信息或内容被应用于FIFO时，由于每个所选站的每个FIFO存储器变为满，旧的信息或内容被移出存储器。 接收设备包括用于使用户能够在所存储的段内向前或向后移动的装置。 提供分区或标记以分离广播内容项，例如在所存储的段内的顺序播放的歌曲，以使得能够向所存储的段内的选定位置进行增量移动。 被选择用于用户处理的存储段的段被复制到用于访问的分离的存储器位置，以避免对所接收的广播信号的连续FIFO存储的干扰。

公开(公告)号：US20030023789A1

公开(公告)日：2003-01-30

申请号：US10175041

申请日：2002-06-20

Inventor： Yung-Chung Chang ,  You-Ming Chiu

IPC: G06F003/00 ,  G06F003/02 ,  G06F003/023 ,  G06F003/05 ,  G06F003/06 ,  G06F005/00

CPC classification number: G06F17/5045

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the Nnull1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the Nnull1th layer, respectively. Then, the number of the buffering devices for the Nnull1th layer is judged whether or not to be 1. If it is, then the buffering device for the Nnull1th layer is connected to the signal source root and the method goes to end. If it is not, the method goes to the step (c). In the step (c), the quantity of the parameter N is added by 1, and then the method repeatedly performs the step (b).

Abstract translation: 提供了一种用于缓冲设备的实现方法，以便将缓冲设备配置在芯片上。 芯片包括信号源根和输出接合焊盘的数量X，其中数字X是正整数。 本发明的实现方法包括：（a）在两个输出接合焊盘之间的靠近中间位置的位置实施用于第N层的缓冲装置，并且将每个输出接合焊盘之一电连接到相应的一个缓冲 第N层的设备。 （b）在第N层的两个缓冲装置之间的靠近中间位置的位置处实施用于第N + 1层的缓冲装置，并且用于第N层的缓冲装置中的每一个电连接到 分别为N + 1层的缓冲装置。 然后，判断N + 1层的缓冲装置的数量是否为1.如果是，则第N + 1层的缓冲装置连接到信号源根，并且该方法结束 。 如果不是，则该方法进行到步骤（c）。 在步骤（c）中，将参数N的数量加1，然后重复执行步骤（b）。

公开(公告)号：US20020188772A1

公开(公告)日：2002-12-12

申请号：US10117455

申请日：2002-04-01

Inventor： Mark Radcliffe ,  Mei Wilson ,  Robert W. Edmiston ,  Brian D. Crites

IPC: G06F003/00 ,  H04N005/445 ,  G06F013/00 ,  G06F003/02 ,  G06F003/023 ,  G06F003/05 ,  G06F003/06 ,  G06F005/00 ,  H04N007/173 ,  H04L012/28 ,  H04L012/56

CPC classification number: H04N21/233 ,  G09B5/00 ,  G09B7/00 ,  G11B27/034 ,  G11B27/34 ,  H04N5/268 ,  H04N5/4401 ,  H04N5/45 ,  H04N7/17318 ,  H04N21/2187 ,  H04N21/234354 ,  H04N21/23439 ,  H04N21/235 ,  H04N21/25825 ,  H04N21/42204 ,  H04N21/4307 ,  H04N21/4316 ,  H04N21/47 ,  H04N21/6125 ,  H04N21/854

Abstract: Various embodiments enable dynamic control of input sources for producing live (and/or archivable) streaming media broadcasts. A user interface can conveniently enable a single individual to produce a streaming media broadcast using a variety of input sources that can be conveniently grouped, selected, and modified on the fly if so desired. User-defined source groups enable an individual to select and arrange source inputs for the streaming media broadcast. In some embodiments, source groups can have properties and behaviors that can be defined by the individual before and even during a broadcast session.

Abstract translation: 各种实施例使得能够动态地控制用于生成直播（和/或可存档）流媒体广播的输入源。 用户界面可以方便地使单个个体能够使用各种输入源产生流媒体广播，如果需要的话可以方便地分组，选择和修改。 用户定义的源组使个人能够选择和排列流媒体广播的源输入。 在一些实施例中，源组可以具有在广播会话之前甚至在广播会话期间由个人定义的属性和行为。

公开(公告)号：US20020126123A1

公开(公告)日：2002-09-12

申请号：US09802458

申请日：2001-03-09

Inventor： Tsung-en Andy Lee

IPC: G06F013/28 ,  G06F005/00 ,  G06F003/06 ,  G06F003/05 ,  G06F003/023 ,  G06F003/02 ,  G06F003/00 ,  G06F012/10

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0674

Abstract: A method of buffer management and task scheduling for two-dimensional data transforming is described. The method includes the steps of reading out old data in a block-by-block pattern and immediately writing in new data in a line-by-line pattern in a buffer using a first mapping scheme. And reading out a following old data in a block-by-block pattern and immediately writing in a following new data in a line-by-line pattern in the buffer using a second mapping scheme. The first and second mapping schemes are interleaved to guarantee output sequences while the buffer is kept full all the time. The buffer thus is maximized, the output flow is continuous and the process loading is smoothed out without loading bursts.

Abstract translation: 描述了用于二维数据变换的缓冲器管理和任务调度的方法。 该方法包括以逐块模式读出旧数据并使用第一映射方案立即以缓冲器中的逐行模式写入新数据的步骤。 并且以逐块模式读出以下旧数据，并使用第二映射方案立即在缓冲器中以逐行模式写入以下新数据。 第一和第二映射方案被交织以保证输出序列，同时缓冲器始终保持充满。 因此，缓冲器最大化，输出流是连续的，并且在不加载突发的情况下平滑处理负载。

公开(公告)号：US20020067192A1

公开(公告)日：2002-06-06

申请号：US10033123

申请日：2001-10-22

Inventor： Heiko Fibranz ,  Eckehard Plnullttner

IPC: H04L007/00 ,  H03L007/00 ,  G06F005/00 ,  G06F003/06 ,  G06F003/05 ,  G06F003/023 ,  G06F003/02 ,  G06F003/00

CPC classification number: G11C7/1006 ,  G11C2207/104 ,  H03K5/135

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract translation: 集成电路具有同步电路和异步电路。 时钟控制输入寄存器电路和用于存储数据的输出寄存器电路各自连接到同步电路和异步电路。 数据从同步电路传送到输入寄存器电路，从它们被传送到异步电路并在异步电路中进行处理。 处理的数据被传送到输出寄存器电路。 序列控制器以取决于异步电路的数据处理持续时间的方式为寄存器电路产生相应的控制时钟信号。 这使得独立于同步电路的时钟频率的同步电路和异步电路之间的高数据吞吐量。

公开(公告)号：US20020065963A1

公开(公告)日：2002-05-30

申请号：US09727270

申请日：2000-11-30

Inventor： Hans-Helge Lehmann ,  Charles E. Shapley ,  Robert A. Smith

IPC: G06F005/00 ,  G06F003/06 ,  G06F003/05 ,  G06F003/023 ,  G06F003/00 ,  G06F003/02 ,  G06F013/00

CPC classification number: G06F13/387

Abstract: A method and system for flexibly and efficiently assigning channel path identifiers (CHPIDs) used by operating system software in computer systems to identify the communication path to I/O devices via channels. To avoid wasted CHPIDs, which may be limited in number, CHPIDs are assigned only to channels which are installed on and configured to the computer system. The CHPIDs may be re-assigned concurrently with ongoing system operations via a user interface and/or an imported, pre-defined CHPID mapping.

Abstract translation: 一种用于灵活有效地分配由计算机系统中的操作系统软件使用的信道路径标识符（CHPID）的方法和系统，以通过信道识别到I / O设备的通信路径。 为了避免浪费的CHPID，数量可能受到限制，CHPID仅分配给安装在计算机系统上并配置到计算机系统的通道。 CHPID可以经由用户接口和/或导入的预定义CHPID映射与正在进行的系统操作同时重新分配。

公开(公告)号：US20020026545A1

公开(公告)日：2002-02-28

申请号：US09855594

申请日：2001-05-16

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC: G06F003/00 ,  G06F003/02 ,  G06F003/023 ,  G06F003/05 ,  G06F003/06 ,  G06F005/00

CPC classification number: G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline stage corresponding to selection of a memory bank and a second pipeline stage corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline stages are effected in parallel, the throughput of the instruction memory can be improved.

Abstract translation: 当从多个存储体中取出指令时，产生对应于存储器组的选择的第一流水线级和对应于指令读出的第二流水线级，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于并行实现第一和第二流水线级，可以提高指令存储器的吞吐量。

公开(公告)号：US20010014922A1

公开(公告)日：2001-08-16

申请号：US09749509

申请日：2000-12-28

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Shigehiro Kuge

IPC: G06F003/00 ,  G06F003/02 ,  G06F003/023 ,  G06F003/05 ,  G06F003/06 ,  G06F005/00

CPC classification number: G06F13/4239 ,  G06F13/1689 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface unit includes a timing control circuit for extracting an effective data window by detecting a point of change in a transferred data, and determining strobe timing for taking in the data in accordance with the extracted effective window; and a strobe clock generating circuit for generating a strobe clock signal for taking in the data under control of the timing control circuit. Regardless of the system structure, accurate data transfer is achieved between any semiconductor devices in the system.

Abstract translation: 接口单元包括定时控制电路，用于通过检测传送数据的变化点来提取有效数据窗口，并根据所提取的有效窗口确定接收数据的选通定时; 以及选通时钟发生电路，用于在定时控制电路的控制下产生用于接收数据的选通时钟信号。 无论系统结构如何，在系统中的任何半导体器件之间实现准确的数据传输。