公开(公告)号：US6433716B2

公开(公告)日：2002-08-13

申请号：US78196501

申请日：2001-02-14

Applicant: DENSO CORP

Inventor： ARAI SOICHIRO ,  ISOMURA HIROFUMI

IPC: G06F3/05 ,  H03M1/12 ,  H03M1/66 ,  H03M1/00

CPC classification number: H03M1/662 ,  H03M1/1225

Abstract: A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter. and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Abstract translation: 用于将模拟数据转换为数字数据或数字数据到模拟数据的数据转换装置由数据转换器组成。 和调解人。 在接收到转换特定数据组的请求时，将多个数据组按组分组地馈送给数据转换器。 如果同时进行多个请求，则中介器在多个请求中进行中介以选择要首先转换的数据组并设置优先顺序。 在调解器中生成与多个请求的组合唯一对应的功能，并且参考表示功能与要选择的请求之间的关系的预先安装的表，基于生成的功能执行中介。

公开(公告)号：US6038273A

公开(公告)日：2000-03-14

申请号：US979670

申请日：1997-11-26

Applicant: Robert J. Hankinson

Inventor： Robert J. Hankinson

IPC: G06T3/40 ,  G06F1/14 ,  G06F3/05 ,  G06F7/02 ,  H04L27/14

CPC classification number: G06T3/40

Abstract: A method and system in which the numeric values to which counters in resampling control circuitry may be reduced. As a result, smaller registers to hold such reduced numeric values may be designed into hardware implementing said circuitry. These smaller registers present savings in processing power and hardware allocation, thereby potentially improving response times and cost efficiency of said hardware.

Abstract translation: 可以减少重新采样控制电路中的计数器的数值的方法和系统。 因此，可以将用于保持这种减小的数值的较小寄存器设计成实现所述电路的硬件。 这些较小的寄存器节省了处理能力和硬件分配，从而潜在地改善了所述硬件的响应时间和成本效率。

公开(公告)号：US5895441A

公开(公告)日：1999-04-20

申请号：US638534

申请日：1996-04-26

Applicant: Christophe Brault ,  Stephane Even ,  Patrick Durand

Inventor： Christophe Brault ,  Stephane Even ,  Patrick Durand

IPC: G01V8/12 ,  G05B13/02 ,  G06F3/05 ,  H03K17/78 ,  H03K17/945 ,  G01R27/00

CPC classification number: H03K17/945 ,  H03K2217/94021

Abstract: A proximity detector including a sensor unit that produces an analog signal and a processor circuit digitizing this signal. The processor circuit includes logic that determines a switching value from an initial value and an extreme value obtained during a learning mode.

Abstract translation: 一种接近检测器，包括产生模拟信号的传感器单元和将该信号数字化的处理器电路。 处理器电路包括从在学习模式期间获得的初始值和极值确定开关值的逻辑。

公开(公告)号：US5894235A

公开(公告)日：1999-04-13

申请号：US936775

申请日：1997-09-24

Applicant: David A. Zimlich

Inventor： David A. Zimlich

IPC: G09G3/20 ,  G06F3/05 ,  G09G3/22 ,  G09G3/36 ,  G11C19/38 ,  G11C27/02 ,  H04L7/033

CPC classification number: G09G3/2011 ,  G06F3/05 ,  G09G3/22 ,  G09G3/3611 ,  G09G3/3685 ,  G11C19/38 ,  G11C27/02 ,  H04L7/0337 ,  G09G3/20

Abstract: A system for sampling an analog or digital data signal at a relatively high rate utilizing relatively slow circuitry. The system includes several sample and hold circuits, each of which receive the data signal. The sample and hold circuits are clocked by respective clock signals that are at the same frequency but equally phased apart from each other. Thus, the sample and hold circuits take samples of the data signal at times that are equally spaced apart from each other. Each of the sample and hold circuits is connected to a series of shift registers that are clocked at the same frequency as the clock used to clock the sample and hold circuit to which they are connected. The shift registers operate to sequentially store samples obtained by their respective sample and hold circuit. The output of the shift registers may be applied to the column drivers of a conventional matrix display.

Abstract translation: 一种利用相对较慢的电路以相对高的速率对模拟或数字数据信号进行采样的系统。 该系统包括几个采样和保持电路，每个采样和保持电路都接收数据信号。 采样和保持电路由相同的时钟信号提供时钟，时钟信号的频率相同，但是彼此相位分开。 因此，采样和保持电路在彼此相等间隔的时间采集数据信号的采样。 每个采样和保持电路连接到一系列移位寄存器，这些移位寄存器的时钟频率与用于对其连接的采样和保持电路进行时钟的时钟频率相同。 移位寄存器用于顺序地存储由它们各自的采样和保持电路获得的采样。 移位寄存器的输出可以应用于常规矩阵显示器的列驱动器。

公开(公告)号：US5808574A

公开(公告)日：1998-09-15

申请号：US798781

申请日：1997-02-11

Applicant: Keith O. Johnson ,  Michael W. Pflaumer

Inventor： Keith O. Johnson ,  Michael W. Pflaumer

IPC: G06F3/05 ,  G06J1/00 ,  G11B20/10 ,  G11B20/22 ,  H03M1/08 ,  H03M1/22 ,  H03M5/04 ,  H04B14/04 ,  H03M1/00

CPC classification number: G11B20/10527 ,  G06J1/00 ,  H03M5/04 ,  H04B14/046

Abstract: An electronic method and apparatus for signal encoding and decoding to provide ultra low distortion reproduction of analog signals, while remaining compatible with industry standardized signal playback apparatus not incorporating the decoding features of the invention, and wherein the improved system provides an interplay of gain, slew rate and wave synthesis operations to reduce signal distortions and improve apparent resolution, all under the control of concealed control codes for triggering appropriate decoding signal reconstruction compensation complementing the signal analysis made during encoding. In addition, signals lacking the encoding process features of the invention are likewise compatible with playback decoders which do embody the invention, to provide some overall restoration enhancement.

Abstract translation: 一种用于信号编码和解码的电子方法和装置，以提供模拟信号的超低失真再现，同时与不结合本发明的解码特征的工业标准化信号重放装置兼容，并且其中改进的系统提供增益，转换的相互作用 速率和波合成操作，以减少信号失真并提高视频分辨率，全部在隐藏控制代码的控制下触发适当的解码信号重建补偿，补充编码期间进行的信号分析。 此外，缺少本发明的编码处理特征的信号同样兼容于实现本发明的回放解码器，以提供一些整体恢复增强。

公开(公告)号：US5805094A

公开(公告)日：1998-09-08

申请号：US667386

申请日：1996-06-21

Applicant: Kevin V. Roach ,  James G. Calvin

Inventor： Kevin V. Roach ,  James G. Calvin

IPC: H03M1/12 ,  G06F3/05 ,  H03M5/08 ,  H03M1/66

CPC classification number: G06F3/05

Abstract: An interface circuit for use with process controllers permits analog signals to be input to a process controller through a binary interface of the process controller and permits analog signals to be output from the process controller through the binary interface. The input analog signal is converted to a digital word of N bits. An identification or end indication and the N bits of the digital word are transmitted to the process controller at a rate selected for compatibility with the scan time of the process controller. The process controller includes a software routine for recognizing the N bits of the digital word. An equivalent approach is used for outputting analog signals through a binary interface of a process controller. The interface circuit can include multiple channels for inputting or outputting multiple analog signals.

Abstract translation: 与过程控制器一起使用的接口电路允许模拟信号通过过程控制器的二进制接口输入到过程控制器，并允许通过二进制接口从过程控制器输出模拟信号。 输入模拟信号被转换成N位的数字字。 识别或结束指示和数字字的N位以选择以与过程控制器的扫描时间兼容的速率发送到过程控制器。 过程控制器包括用于识别数字字的N位的软件程序。 使用等效方法通过过程控制器的二进制接口输出模拟信号。 接口电路可以包括用于输入或输出多个模拟信号的多个通道。

公开(公告)号：US5773900A

公开(公告)日：1998-06-30

申请号：US793285

申请日：1997-05-20

Applicant: Hartmut Schumacher ,  Klaus Oswald ,  Norbert Crispin ,  Martin Daiber

Inventor： Hartmut Schumacher ,  Klaus Oswald ,  Norbert Crispin ,  Martin Daiber

IPC: G01P15/00 ,  B60R21/01 ,  B60R21/16 ,  G01D3/028 ,  G01P15/08 ,  G01P15/09 ,  G06F3/05 ,  H03M1/08 ,  H03M1/12 ,  B60L3/00

CPC classification number: B60R21/01 ,  G01P15/08 ,  G01P15/09 ,  G06F3/05

Abstract: A device for suppressing interference signals for a microprocessor evaluating a plurality of sensor signals on respective input lines coupled thereto. Each of the input lines is selectively coupled to a first resistance during a measurement interval and selectively coupled to a second resistance during an interval outside of the measurement interval.

Abstract translation: PCT No.PCT / DE95 / 01082 Sec。 371日期1997年5月20日 102（e）日期1997年5月20日PCT提交1995年8月17日PCT公布。 出版物WO96 / 07872 日期：1996年3月14日一种用于抑制微处理器评估耦合到其上的相应输入线上的多个传感器信号的干扰信号的装置。 在测量间隔期间，每个输入线选择性地耦合到第一电阻，并且在测量间隔之外的间隔期间选择性地耦合到第二电阻。

公开(公告)号：US5758138A

公开(公告)日：1998-05-26

申请号：US576943

申请日：1995-12-22

Applicant: Robert J. Hankinson

Inventor： Robert J. Hankinson

IPC: G06T3/40 ,  G06F1/14 ,  G06F3/05 ,  G06F7/02

CPC classification number: G06T3/40

Abstract: A method and system in which the numeric values to which counters in resampling control circuitry may be reduced. As a result, smaller registers to hold such reduced numeric values may be designed into hardware implementing said circuitry. These smaller registers present savings in processing power and hardware allocation, thereby potentially improving response times and cost efficiency of said hardware.

Abstract translation: 可以减少重新采样控制电路中的计数器的数值的方法和系统。 因此，可以将用于保持这种减小的数值的较小寄存器设计成实现所述电路的硬件。 这些较小的寄存器节省了处理能力和硬件分配，从而潜在地改善了所述硬件的响应时间和成本效率。

公开(公告)号：US5721830A

公开(公告)日：1998-02-24

申请号：US527668

申请日：1995-09-12

Applicant: Han C. Yeh ,  Peter C. Chen

Inventor： Han C. Yeh ,  Peter C. Chen

IPC: G06F3/05 ,  G06F13/00 ,  H03M1/66 ,  H04L13/08 ,  H04L29/14 ,  H04M11/00 ,  H04M11/06

CPC classification number: H04M11/06 ,  H04L69/40

Abstract: An HSP communications system contains a host computer which executes a software modem program and a device containing a circular buffer and a D/A converter. Typically, the host executes update routines in response to interrupts from the device and writes to the circular buffer digital samples representing amplitudes of an analog signal complying with a desired communication protocol. The samples pass through the circular buffer to the D/A converter which converts the samples into an analog communication signal. In environments such as multi-tasking systems, the host may occasionally skip interrupts and not provide new samples when required. In this case, the D/A converter reuses samples in the circular buffer to generate a maintenance signal. The maintenance signal typically does not convey correct data but is sufficient to maintain a communication link and prevent a remote device from disconnecting or entering a retrain mode. To provide a smoother maintenance signal, the circular buffer's size contains samples for an integral number of periods at the carrier and baud frequency of the desired protocol. Error correction and retransmission replace incorrect or lost data.

Abstract translation: HSP通信系统包含执行软件调制解调器程序的主计算机和包含循环缓冲器和D / A转换器的设备。 通常，主机响应于来自设备的中断执行更新例程，并写入表示符合所需通信协议的模拟信号幅度的循环缓冲器数字样本。 样本通过循环缓冲器到D / A转换器，D / A转换器将样本转换成模拟通信信号。 在诸如多任务系统的环境中，主机可能偶尔跳过中断，并且在需要时不提供新的采样。 在这种情况下，D / A转换器重复使用循环缓冲器中的采样以产生维护信号。 维护信号通常不传送正确的数据，但足以维持通信链路并防止远程设备断开或进入重新训练模式。 为了提供更平滑的维护信号，循环缓冲器的大小包含在载波上的整数个周期的样本和所需协议的波特率。 纠错和重传代替不正确或丢失的数据。

公开(公告)号：US5696504A

公开(公告)日：1997-12-09

申请号：US689068

申请日：1996-07-30

Applicant: Ernesto Vidal Oliveros

Inventor： Ernesto Vidal Oliveros

IPC: G06F3/023 ,  G06F3/05 ,  H03K17/94

CPC classification number: G06F3/023 ,  G06F3/0219 ,  G06F3/0235 ,  G06F3/05

Abstract: An encoding method employs sixteen basic values, twelve numerical magnitudes and four directional modifiers. These values are the result combining binary digits in sets of 4 bits. The encoding method is utilized for encoding letters, symbols and programming commands. Letters are defined as numerical magnitudes altered by a directional modifier, symbols and commands are addressed as numerical magnitudes altered by two or more directional modifiers. An analog to digital encoding technique converts analog data into binary form by means of "breaking" an analog wave into a multitude of periodic waves, each wave with a particular wave-break, wave length and amplitude, supplying hence, an efficient and economical method for processing and storing binary information. An analog device describes the particular position of the sun at a given time, supplying therefor an apparatus that not only measures time but also describes space.

Abstract translation: 编码方法采用十六个基本值，十二个数值和四个方向修正。 这些值是组合4位的二进制数字的结果。 编码方法用于编码字母，符号和编程命令。 字母被定义为通过方向修饰符改变的数字量值，符号和命令被解决为由两个或更多个定向修饰符改变的数值幅度。 模拟数字编码技术通过将模拟波“断开”成多个周期波，每个波具有特定的波浪断裂，波长和幅度，将模拟数据转换为二进制形式，从而提供了一种高效和经济的方法 用于处理和存储二进制信息。 模拟设备描述了在给定时间的太阳的特定位置，为其提供不仅测量时间而且还描述空间的设备。