公开(公告)号：US07068685B1

公开(公告)日：2006-06-27

申请号：US09979207

申请日：2000-05-23

Applicant: Tuomo Sihvola

Inventor： Tuomo Sihvola

IPC: H04J3/07

CPC classification number: H04J3/0608 ,  H04J3/1611 ,  H04J2203/006

Abstract: The invention relates to a method for finding frame alignment and accepting and monitoring TTI identifiers contained in frames in an SDH system. Advantageously the method according to the invention comprises steps in which frame alignment is first sought for by means of a frame alignment signal. When frame alignment has been found, it is monitored that it stays correct and at the same time at least one TTI identifier is read. According to the invention, at least one TTI identifier is saved from a frame after the finding of frame alignment. If a loss of frame alignment is detected, the TTI identifier saved is stored for a predetermined time. The invention further relates to an arrangement comprising means to implement the method described above in an SDH system.

Abstract translation: 本发明涉及一种用于查找帧对齐和接收和监视包含在SDH系统中的帧中的TTI标识符的方法。 有利地，根据本发明的方法包括首先通过帧对准信号寻求帧对准的步骤。 当发现帧对齐时，监视它保持正确，同时读取至少一个TTI标识符。 根据本发明，在帧对准的发现之后，从帧中保存至少一个TTI标识符。 如果检测到帧对准丢失，则保存的TTI标识符被存储预定时间。 本发明还涉及一种包括用于在SDH系统中实现上述方法的装置的装置。

公开(公告)号：US20060133427A1

公开(公告)日：2006-06-22

申请号：US11003847

申请日：2004-12-03

Applicant: Kenneth Wolf ,  Michael Vernal ,  Christopher Kaler ,  Elliot Waingold ,  Eric Christensen ,  Jeffrey Schlimmer ,  Martin Gudgin ,  Siddhartha Puri

Inventor： Kenneth Wolf ,  Michael Vernal ,  Christopher Kaler ,  Elliot Waingold ,  Eric Christensen ,  Jeffrey Schlimmer ,  Martin Gudgin ,  Siddhartha Puri

IPC: H04J3/07

CPC classification number: G06F17/2247 ,  G06F17/2258 ,  H04L67/02 ,  H04L69/08 ,  H04L69/329

Abstract: A mechanism for sending structured data using a corresponding byte stream. Upon accessing structured data such as a Simple Object Access Protocol (SOAP) envelope, a byte stream is generated. The byte stream includes bytes that represent the structured data, as well as a collection of bytes that represents properties about the byte stream such as, for example, a mode of communication. The byte stream may then be passed to a communication module (e.g., a TCP or Named Pipes module) capable of receiving and transmitting the byte stream.

公开(公告)号：US07027465B2

公开(公告)日：2006-04-11

申请号：US10167986

申请日：2002-06-11

Applicant: Petri Hautala

Inventor： Petri Hautala

IPC: H04J3/07

CPC classification number: H04W72/1289 ,  H04L1/0086 ,  H04L69/22 ,  H04W72/1242 ,  H04W72/1284 ,  H04W84/12

Abstract: The invention discloses a method for detecting priority of data frames comprising the steps of extracting (S1) a bit pattern from a predetermined position in a frame, comparing (S2, S3) the extracted bit pattern with a search pattern, and identifying (S4) the received frame as a priority frame in case the extracted bit pattern (BP) matches with the first search pattern (SP). By this method, the priority of a data frame can easily be detected. The invention also proposes a corresponding device for detecting priority of data frames.

Abstract translation: 本发明公开了一种检测数据帧的优先级的方法，包括以下步骤：从帧中的预定位置提取（S 1）比特模式，将提取的比特模式与搜索模式进行比较（S 2，S 3），以及识别 （S）在所提取的位模式（BP）与第一搜索模式（SP）匹配的情况下，将接收的帧作为优先级帧。 通过该方法，可以容易地检测数据帧的优先级。 本发明还提出了一种用于检测数据帧的优先级的相应设备。

公开(公告)号：US06999424B1

公开(公告)日：2006-02-14

申请号：US09489681

申请日：2000-01-24

Applicant: Branko Kovacevic ,  Kevork Kechichian

Inventor： Branko Kovacevic ,  Kevork Kechichian

IPC: H04L12/28 ,  H04J1/00 ,  H04J3/07 ,  G06F15/16 ,  G06F15/167

CPC classification number: H04N21/23424 ,  H04N21/44016

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream. In another embodiment, the hardware is used to implement a splicing of streams of data.

Abstract translation: 根据本发明的具体方面，诸如MPEG-2视频流的压缩视频流由传输解复用器接收，被同步，被解析成单独的分组类型，并被写入到解复用器外部的缓冲器位置。 适应字段由单独的解析器处理。 此外，主基本流数据可以基于主基本流的分组标识符由单独的主要基本流解析器来处理。 视频数据包可以基于流标识符值进行解析。 基于分配表信息，通过输出控制器将特定数据分组存储在一个或多个系统存储器或视频存储器缓冲器中。 与特定基本流或分组适配字段相关联的私有数据被重新分组，并被写入输出缓冲器位置。 在具体实现中，与系统相关联的硬件用于获取数据流，而不知道流的特定协议。 在另一个实施例中，硬件用于实现数据流的拼接。

公开(公告)号：US06973101B1

公开(公告)日：2005-12-06

申请号：US09768900

申请日：2001-01-24

Applicant: Edward L. Grivna

Inventor： Edward L. Grivna

IPC: G11C7/10 ,  H04J3/06 ,  H04J3/07

CPC classification number: G11C7/1006 ,  H04J3/0605

Abstract: An apparatus comprising a memory, an encoder and one or more registers. The memory may be configured to (i) read and/or write a plurality of state vectors and (ii) read and/or write data. The encoder may be configured to present state vectors to be written in response to (i) data read from the memory (ii) a first address and (iii) a serial data stream. The registers may be configured to present the first address in response to an input address.

Abstract translation: 一种包括存储器，编码器和一个或多个寄存器的装置。 存储器可以被配置为（i）读取和/或写入多个状态向量和（ii）读取和/或写入数据。 编码器可以被配置为响应于（i）从存储器（ii）读取第一地址的数据和（iii）串行数据流来呈现待写入的状态向量。 寄存器可以被配置为响应于输入地址呈现第一地址。

公开(公告)号：US20050228911A1

公开(公告)日：2005-10-13

申请号：US10510659

申请日：2003-04-14

Applicant: Thomas Fuehrer ,  Robert Hugel

Inventor： Thomas Fuehrer ,  Robert Hugel

IPC: H04L12/40 ,  B60R16/02 ,  G06F12/16 ,  G06F13/42 ,  H04J3/07 ,  H04L12/407 ,  H04L12/413 ,  H04L25/38

CPC classification number: H04J3/07 ,  H04L49/90 ,  H04L2012/40215

Abstract: A method and device are described for padding segments for transmitting data on a bus system and a bus system. The segments have a predetermined total number of bytes and the data being transmitted in segments, in the event of a transmission of data including fewer bytes than the predetermined total number of the segment, the missing bytes of the data being padded to the total number of the segment by a filling pattern of a corresponding byte number, distinguished in that a filling pattern, whose byte number corresponds to the total number of the segment, is first written into the segment and the bytes of the data are subsequently written into the same segment, the particular bytes of the filling pattern being overwritten by the bytes of the data.

Abstract translation: 描述了用于在总线系统和总线系统上传输数据的填充段的方法和装置。 在包含比该段的预定总数少的字节的数据的传输的情况下，这些段具有预定的总字节数，并且数据被分段传送，所述数据的丢失字节被填充到总数 该段通过相应字节号的填充模式，区分为其字节数对应于段的总数的填充模式首先被写入段，并且数据的字节随后被写入同一段 ，填充模式的特定字节被数据的字节覆盖。

公开(公告)号：US06882661B1

公开(公告)日：2005-04-19

申请号：US09662157

申请日：2000-09-14

Applicant: Tadhg Creedon ,  Denise De Paor ,  Fergus Casey

Inventor： Tadhg Creedon ,  Denise De Paor ,  Fergus Casey

IPC: H04L7/02 ,  H04L7/04 ,  H04Q11/04 ,  H04J3/07

CPC classification number: H04Q11/0421 ,  H04L7/02 ,  H04L2007/045 ,  H04Q2213/13103 ,  H04Q2213/13174 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/1336

Abstract: A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.

Abstract translation: 系统将包括由非分组字分离的数据分组的数据流从第一时钟域传送到第二时钟域。 它包括弹性缓冲器，数据流在第一时钟域中的时钟频率的控制下以循环序列写入到该弹性缓冲器中，并且在时钟频率的控制下以循环序列读出数据流 第二个域名 监视两个序列以提供指示读取序列接近写入序列的预期信号。 非分组字被插入到第一域中的数据流中。 在第二时钟域中，检测插入的非分组字的存在，并使缓冲器推进读取周期，从而丢弃所插入的非分组字。

公开(公告)号：US20050002403A1

公开(公告)日：2005-01-06

申请号：US10609562

申请日：2003-07-01

Applicant: Kim Roberts ,  James Harley ,  Philippe Neusy ,  Michael Mayer

Inventor： Kim Roberts ,  James Harley ,  Philippe Neusy ,  Michael Mayer

IPC: H04J3/06 ,  H04J3/07 ,  H04L12/28

CPC classification number: H04J3/076

Abstract: In a method of estimating a bit rate (f1) of a digital signal conveyed through a SONET network between an originating node and a terminating node, the digital signal received by the originating node is processed to determine a result of a first function of the signal bit rate (f1) and a respective Tx local reference frequency (f2) of the originating node. A result of a second function of the Tx local reference frequency (f2) and a respective Rx local reference frequency (f3) of the terminating node is calculated. Finally, a result of a third function of the respective first and second function results is calculated, to derive an estimate of the signal bit rate (f4) relative to the Rx local reference frequency (f3).

Abstract translation: 在估计通过始发节点和终止节点之间的SONET网络传送的数字信号的比特率（f1）的方法中，处理由始发节点接收的数字信号以确定信号的第一功能的结果 比特率（f1）和相应的Tx本地参考频率（f2）。 计算终端节点的Tx本地参考频率（f2）和相应Rx本地参考频率（f3）的第二功能的结果。 最后，计算相应的第一和第二功能结果的第三功能的结果，以导出相对于Rx本地参考频率（f3）的信号比特率（f4）的估计。

公开(公告)号：US6160816A

公开(公告)日：2000-12-12

申请号：US902277

申请日：1997-07-29

Applicant: Kazuo Tanaka ,  Eiji Shimose

Inventor： Kazuo Tanaka ,  Eiji Shimose

IPC: H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04J3/12 ,  H04Q3/42 ,  H04Q11/04

CPC classification number: H04J3/07 ,  H04J3/0685 ,  H04J3/12 ,  H04Q11/0471 ,  H04Q2213/13103 ,  H04Q2213/13214

Abstract: A first group of asynchronous clock converters effect the conversion between a DNE clock and an RDT clock to which DS-0 data and signalling data are synchronized, for the data items which are transferred between a cross-connector and a DNE. A second group of asynchronous clock converters effect the conversion between a CPE clock and the RDT clock to which DS-0 data and signalling data are synchronized, for the data items which are transferred between the cross-connector and a CPE. As a result, cross-connect processes based on the single RDT clock are realized, and loop timings are guaranteed for the DNE and the CPE.

Abstract translation: 第一组异步时钟转换器对于在交叉连接器和DNE之间传输的数据项，会影响DNE时钟与DS-0数据和信令数据同步的RDT时钟之间的转换。 第二组异步时钟转换器影响在交叉连接器和CPE之间传输的数据项之间的CPE时钟与DS-0数据和信号数据同步的RDT时钟之间的转换。 因此，实现了基于单个RDT时钟的交叉连接过程，并为DNE和CPE保证了循环定时。

公开(公告)号：US06157659A

公开(公告)日：2000-12-05

申请号：US995414

申请日：1997-12-19

Applicant: Peter Dane Bird

Inventor： Peter Dane Bird

IPC: H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04J3/16 ,  H04L12/66

CPC classification number: H04J3/1641 ,  H04J3/0632 ,  H04J3/073

Abstract: Multiplexing and demultiplexing are commonplace for an efficient bandwidth utilization in telecommunications. SRTS (Synchronous Residual Time Stamp) technique is widely used for timing recovery in processing of digital signal streams. The bit stuffing is also prevalent for various purposes, one being rate adjustment. The invention performs the SRTS technique entirely digitally to monitor the rate of slower speed signal streams in relation to the rate of a higher speed stream. The digital implementation permits the use of context switching for processing a plurality of digital signal streams. As the result, hardware requirement is greatly reduced.

Abstract translation: 多路复用和解复用是电信中有效带宽利用的常用方法。 SRTS（同步残留时间戳）技术广泛应用于数字信号流处理中的定时恢复。 位填充对于各种目的也是普遍的，一种是速率调整。 本发明完全数字地执行SRTS技术以监测与较高速度流的速率相关的较慢速度信号流的速率。 数字实现允许使用上下文切换来处理多个数字信号流。 结果，硬件要求大大降低。