公开(公告)号：US20230113197A1

公开(公告)日：2023-04-13

申请号：US17498048

申请日：2021-10-11

申请人： Xilinx, Inc.

发明人： Amit Kasat ,  Tharun Kumar Ksheerasagar ,  Hemant Kashyap ,  Madhusudana Reddy ,  Rohit Bhadana

IPC分类号： G06F30/3308 ,  G06F30/323

摘要： Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

公开(公告)号：US20230050757A1

公开(公告)日：2023-02-16

申请号：US17399523

申请日：2021-08-11

申请人： Xilinx, Inc.

发明人： Stephen Andrew Neuendorffer ,  Jianyi Cheng

IPC分类号： G06F30/323 ,  G06F30/343

摘要： Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

公开(公告)号：US20220405457A1

公开(公告)日：2022-12-22

申请号：US17476615

申请日：2021-09-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

IPC分类号： G06F30/392 ,  G06F30/398 ,  G06F30/323

摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

公开(公告)号：US11520966B2

公开(公告)日：2022-12-06

申请号：US17370976

申请日：2021-07-08

申请人： Tektronix, Inc.

发明人： David Everett Burgess

IPC分类号： G06F30/367 ,  G06F30/3953 ,  G06F30/398 ,  G06F30/323 ,  G06F30/333 ,  G06F30/3308 ,  G01R31/3183 ,  G06F119/02

摘要： A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

公开(公告)号：US11501044B1

公开(公告)日：2022-11-15

申请号：US17132943

申请日：2020-12-23

申请人： Cadence Design Systems, Inc.

发明人： Shirin Farrahi ,  Yang Lu

IPC分类号： G06F30/30 ,  G06F30/323 ,  G06F30/337 ,  G06F30/327 ,  G06F30/20

摘要： Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

公开(公告)号：US20220300688A1

公开(公告)日：2022-09-22

申请号：US17693236

申请日：2022-03-11

申请人： Synopsys, Inc.

发明人： Peter Moceyunas ,  Jiong Luo ,  Luca Amaru ,  The Casey ,  Jovanka Ciric Vujkovic ,  Patrick Vuillod

IPC分类号： G06F30/327 ,  G06F30/323

摘要： A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

公开(公告)号：US20220284159A1

公开(公告)日：2022-09-08

申请号：US17827670

申请日：2022-05-28

申请人： UNIGROUP SPREADTRUM COMMUNICATIONS (HUIZHOU) CO., LTD.

发明人： Qi TAN

IPC分类号： G06F30/31 ,  G06F30/323

摘要： A method, an apparatus, and a system for checking a schematic circuit diagram are provided. The method includes: determining a netlist file and a bill of material (BOM) list of the schematic circuit diagram, where the schematic circuit diagram is drawn by an electronic design automation (EDA) tool; and determining whether parts in the schematic circuit diagram are in a preset part list and determining whether connection relationships among the parts meet preset connection relationships, according to the netlist file and the BOM list, to obtain a check result, where the preset part list includes standard part information of multiple parts.

公开(公告)号：US20220198112A1

公开(公告)日：2022-06-23

申请号：US17548110

申请日：2021-12-10

申请人： XEPIC CORPORATION LIMITED

发明人： Jinya ZHANG

IPC分类号： G06F30/3308 ,  G06F30/323

摘要： The present disclosure provides methods and devices for simulating a design, wherein the design comprises a main class with parameters and a plurality of instances of the main class, wherein the plurality of instances comprise a first instance and a second instance. The method includes: determining, by analyzing the design, a plurality of secondary classes associated with instantiating the main class, wherein the plurality of secondary classes are used as the parameters of the main class and comprise a first secondary class corresponding to the first instance and a second secondary class corresponding to the second instance; translating the design to generate a first temporary code associated with the plurality of instances; generating, based on the first temporary code, a plurality of instance machine codes corresponding to the plurality of instances; and simulating the design based on the plurality of instance machine codes.

公开(公告)号：US11361133B2

公开(公告)日：2022-06-14

申请号：US15715795

申请日：2017-09-26

申请人： Intel Corporation

发明人： Dmitry N. Denisenko

IPC分类号： G06F30/327 ,  G06F8/41 ,  G06F30/34 ,  G06F30/3312 ,  G06F30/323 ,  G06F117/08

摘要： Methods and apparatus for implementing a programmable integrated circuit using circuit design tools are provided. The circuit design tools may receive a high-level synthesis source code, parse the high-level synthesis source code to generate a compiler intermediate representation, process the compiler intermediate representation to generate a register transfer level (RTL) description, and then synthesize and compile the RTL description to generate an output netlist. Timing analysis may be performed on the output netlist to identify a critical path. Components in the critical path may be mapped back to specific portions in the RTL descriptions, to specification portions of the compiler intermediate representation, and to specific lines in the high-level synthesis source code. The designer can then optimize the high-level synthesis source code to shorten the critical path. This process may be iterated as many times as desired.

公开(公告)号：US20220180033A1

公开(公告)日：2022-06-09

申请号：US17457187

申请日：2021-12-01

申请人： Synopsys, Inc.

发明人： Gaurav Kumar VERMA ,  Krishna Menon MATHILAKATH ,  Mayank GUPTA ,  Vivek GAUR

IPC分类号： G06F30/3308 ,  G06F30/323 ,  G06F30/39

摘要： Techniques for improved analysis and simulation of an IC design are disclosed. Simulation activity for an integrated circuit (IC) design is identified using one or more processors. One or more potential improvements to a simulation of the IC design are generated based on the simulation activity, the one or more potential improvements relating to at least one of signal activity or process activity, during simulation, reflected in the simulation activity. A hardware description language (HDL) design file corresponding to the IC design is modified to indicate the one or more potential improvements to the simulation.