公开(公告)号：US20200074019A1

公开(公告)日：2020-03-05

申请号：US16556600

申请日：2019-08-30

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Eleonora Testa ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F17/50

摘要： Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

公开(公告)号：US11669665B1

公开(公告)日：2023-06-06

申请号：US17527911

申请日：2021-11-16

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Vinicius Neves Possani ,  Eleonora Testa ,  Felipe dos Santos Marranghello ,  Christopher Casares ,  Jiong Luo ,  Patrick Vuillod

IPC分类号： G06F30/327 ,  G06F30/343 ,  G06F30/323 ,  G06F30/337 ,  G06F30/34 ,  G06F30/373 ,  G06F30/398 ,  H03K19/17 ,  H03K19/173 ,  H03K19/17728

CPC分类号： G06F30/327 ,  G06F30/343 ,  H03K19/1731 ,  H03K19/17728 ,  G06F30/323 ,  G06F30/337 ,  G06F30/34 ,  G06F30/373 ,  G06F30/398

摘要： A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.

公开(公告)号：US11010511B2

公开(公告)日：2021-05-18

申请号：US16556600

申请日：2019-08-30

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Eleonora Testa ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F30/00 ,  G06F30/20 ,  G06F30/25 ,  G06F30/327

摘要： Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

公开(公告)号：US20220300688A1

公开(公告)日：2022-09-22

申请号：US17693236

申请日：2022-03-11

申请人： Synopsys, Inc.

发明人： Peter Moceyunas ,  Jiong Luo ,  Luca Amaru ,  The Casey ,  Jovanka Ciric Vujkovic ,  Patrick Vuillod

IPC分类号： G06F30/327 ,  G06F30/323

摘要： A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

公开(公告)号：US11120184B2

公开(公告)日：2021-09-14

申请号：US16904077

申请日：2020-06-17

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Jiong Luo ,  Patrick Vuillod

IPC分类号： G06F30/327 ,  G06F30/31 ,  G06F119/16

摘要： A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.

公开(公告)号：US20180239846A1

公开(公告)日：2018-08-23

申请号：US15962561

申请日：2018-04-25

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5081 ,  G06F17/509 ,  G06F2217/84

摘要： Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

公开(公告)号：US10740517B1

公开(公告)日：2020-08-11

申请号：US16125472

申请日：2018-09-07

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F30/327

摘要： Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.

公开(公告)号：US10325051B2

公开(公告)日：2019-06-18

申请号：US15962561

申请日：2018-04-25

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F17/50

摘要： Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

公开(公告)号：US10049174B2

公开(公告)日：2018-08-14

申请号：US15382406

申请日：2016-12-16

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

公开(公告)号：US20180173818A1

公开(公告)日：2018-06-21

申请号：US15382406

申请日：2016-12-16

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Patrick Vuillod ,  Jiong Luo

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031

摘要： Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.