公开(公告)号：US20140035644A1

公开(公告)日：2014-02-06

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Chittoor PARTHASARATHY ,  Nitin CHAWLA ,  Kallol CHATTERJEE ,  Pascal URARD

IPC: H03K3/02

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20130285708A1

公开(公告)日：2013-10-31

申请号：US13931343

申请日：2013-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Vinod KUMAR

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

公开(公告)号：US20130169311A1

公开(公告)日：2013-07-04

申请号：US13675307

申请日：2012-11-13

Applicant: STMicroelectronics International N.V.

Inventor： Sushrant MONGA

IPC: H03K19/00

CPC classification number: H03K19/0005 ,  H04L25/0278 ,  H04L25/028

Abstract: An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system.

Abstract translation: 用于传输线的缓冲器的实施例，包括这种缓冲器的电路，高速数据链路和低压差分信号（LVDS）系统。

公开(公告)号：US20250167775A1

公开(公告)日：2025-05-22

申请号：US18921440

申请日：2024-10-21

Applicant: STMicroelectronics International N.V.

Inventor： Francesco Ciappa ,  Alberto Bianco ,  Riccardo Peloso

IPC: H03K5/02 ,  H03K4/06

Abstract: The disclosure pertains to adaptive wake-up threshold generation in variable power supplies, particularly applicable to USB-PD chargers and wireless charging devices with digital controllers. It addresses the problem of power consumption during zero-load conditions in burst mode operation. The invention comprises a circuit with a processor, a GPIO pin, and a wake-up threshold generator. The processor drives a signal generator in burst mode, alternating between wake-up phases and waiting intervals. The GPIO pin is set to different states based on the wake-up threshold's relation to predefined bounds. The wake-up threshold generator adjusts the threshold in response to the GPIO pin's state. This adaptive approach enables efficient power management by allowing deep sleep during waiting times while maintaining responsiveness to varying output voltages, thus improving overall system efficiency in variable power supply applications.

公开(公告)号：US20250167041A1

公开(公告)日：2025-05-22

申请号：US18516501

申请日：2023-11-21

Applicant: STMicroelectronics International N.V.

Inventor： Fabrizio Fausto Renzo TOIA ,  Daniele CAPELLI ,  Samuele SCIARRILLO

IPC: H01L21/768 ,  H01L23/528

Abstract: A process that helps ensure uniform height of conductive structures formed among intermetal dielectric layers of a wafer. When a metal layer is deposited on a first intermetal dielectric layer, a sealing layer is formed on the metal layer either before or after the metal layer is patterned to form metal interconnect structures. A first interlevel dielectric sub-layer is then formed on the sealing layer. A chemical mechanical planarization (CMP) process is then performed on the first interlevel dielectric sub-layer using the sealing layer as an etch stop. A second interlevel dielectric sub-layer is then formed on the first interlevel dielectric sub-layer.

公开(公告)号：US20250149991A1

公开(公告)日：2025-05-08

申请号：US18500343

申请日：2023-11-02

Applicant: STMicroelectronics International N.V.

Inventor： Claudio Adragna

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

Abstract: According to an embodiment, a method is proposed that includes sensing a reverse current through a main switch of an active clamp flyback (ACF) converter. The ACF converter includes a flyback transformer and an auxiliary switch. The method further includes determining whether a sense voltage corresponding to the reverse current exceeds a threshold; decreasing a duration for the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration that the auxiliary switch is activated; increasing the duration by a second incremental time interval greater than the first incremental time interval, the increasing being in response to the reverse current not exceeding the threshold; and activating the auxiliary switch for the duration to achieve zero voltage switching (ZVS).

公开(公告)号：US20250142864A1

公开(公告)日：2025-05-01

申请号：US18385067

申请日：2023-10-30

Applicant: STMicroelectronics International N.V.

Inventor： Ferdinando IUCOLANO ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA ,  Giovanni GIORGINO ,  Aurore CONSTANT ,  Virgil GUILLON

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Methods, systems, and apparatuses for normally off HEMT are provided, including for in situ plasma treatment before Al2O3 deposition for improved on on-hydrogen-based resistance. An exemplary method may include providing a wafer comprising a AlGaN layer and a p-GaN layer; etching the p-GaN layer to form a p-GaN gate; depositing a first aluminum oxide layer over the p-GaN gate; depositing a silicon dioxide layer over the aluminum layer; etching the silicon dioxide layer and the aluminum oxide layer to expose a first portion of the AlGaN layer starting a first distance from the p-GaN gate; treating the first portion of the AlGaN layer with an in-situ hydrogen-based plasma treatment, wherein the in situ plasma treatment deactivates magnesium in the first portion of the AlGaN layer; and forming at least a first normally-off HEMT, wherein the gate of the normally-off HEMT is the first p-GaN gate.

公开(公告)号：US20250142225A1

公开(公告)日：2025-05-01

申请号：US18494502

申请日：2023-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Jeffrey M. Raynor

IPC: H04N25/531 ,  H04N23/71 ,  H04N23/73 ,  H04N25/57 ,  H04N25/78

Abstract: According to an embodiment, a method for capturing an image frame using a pixel array of an image sensor is provided. The method includes sequentially resetting each pixel row of the pixel array; sequentially reading out each pixel row of a first subset of pixel rows during a readout phase such that an integration time for each pixel of the first subset of pixel rows is equal to a fixed integration time; and globally resetting pixels of the pixel array in response to detecting that an ambient light level exceeds a threshold level, the globally resetting of the pixels occurring before a reading out of a second subset of pixel rows, each pixel row in the second subset of pixel rows having a variable integration time less than the fixed integration time and starting from the globally resetting of the pixels.

公开(公告)号：US20250137841A1

公开(公告)日：2025-05-01

申请号：US18926250

申请日：2024-10-24

Applicant: STMicroelectronics International N.V.

Inventor： William HALLIDAY ,  Brandon Scott JOHNSON ,  Fraser WILLIAMS ,  Garrie VICKERS ,  Andrew John PRICE ,  Axel CROCHERIE ,  Yandong MAO ,  Fabrice MARTIN ,  Tat Ming TEO ,  Vincent BEIX ,  Justin CATANIA

IPC: G01J1/02 ,  G01J1/04 ,  G01J1/44

Abstract: Example embodiments of the present disclosure provide an optical module sensor. An example optical module sensor may include an optical radiation-emitting device, a reference, an optical radiation receiver positioned, an electromagnetic interference shield, and a housing cap. The housing cap may include a barrier wall positioned such that the housing cap defines a transmission cavity and a receiving cavity. The optical radiation-emitting device and the reference sensor may be positioned within the transmission cavity and the optical radiation receiver may be positioned within the receiving cavity. The housing cap may include an attenuation wall positioned between the reference sensor and the optical radiation receiver.

公开(公告)号：US20250132893A1

公开(公告)日：2025-04-24

申请号：US18910731

申请日：2024-10-09

Applicant: STMicroelectronics International N.V.

Inventor： Pierre-Alexandre BLANC ,  Benjamin SARTORI

IPC: H04L9/06 ,  G06F7/58

Abstract: The present description concerns a method of verification, implemented by an electronic device, of a matrix used for the implementation of a data cipher algorithm comprising, for the generation of the matrix, the use of a first function and of a second function, the verification method comprising a verification using a final portion of the output data of the first function.