公开(公告)号：US20220187896A1

公开(公告)日：2022-06-16

申请号：US17568354

申请日：2022-01-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg Sadowski

IPC: G06F1/3228 ,  G06F1/3296 ,  G06F11/34 ,  G06N20/00

Abstract: A processing unit includes a plurality of components configured to execute instructions and a controller. The controller is configured to determine a power consumption of the processing unit, determine a waiting status of the processing unit based on waiting statuses of components, and selectively modify an operating state of the processing unit based on the waiting status and the power consumption of the processing unit. In some cases, the operating state is modified in response to a percentage of the components that are waiting for an action to complete being below a threshold percentage and the power consumption of the processing unit being below a power limit. In some cases, the controller identifies a pattern in the power consumption by the processing unit and modifies the operating state of the processing unit to increase the power consumption of the processing unit based on the pattern identified by the controller.

公开(公告)号：US11360891B2

公开(公告)日：2022-06-14

申请号：US16355168

申请日：2019-03-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/0802 ,  G06F12/084 ,  G06F12/0846

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

公开(公告)号：US20220179741A1

公开(公告)日：2022-06-09

申请号：US17116952

申请日：2020-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ross V. La Fetra

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/45

Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

公开(公告)号：US20220171635A1

公开(公告)日：2022-06-02

申请号：US17673647

申请日：2022-02-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Tony Tye ,  Brian Laird Sumner ,  Konstantin Zhuravlyov

IPC: G06F9/445 ,  G06F8/76

Abstract: Described herein are techniques for executing a heterogeneous code object executable. According to the techniques, a loader identifies a first memory appropriate for loading a first architecture-specific portion of the heterogeneous code object executable, wherein the first architecture specific portion includes instructions for a first architecture, identifies a second memory appropriate for loading a second architecture-specific portion of the heterogeneous code object executable, wherein the second architecture specific portion includes instructions for a second architecture that is different than the first architecture, loads the first architecture-specific portion into the first memory and the second architecture-specific portion into the second memory, and performs relocations on the first architecture-specific portion and on the second architecture-specific portion.

公开(公告)号：US11347925B2

公开(公告)日：2022-05-31

申请号：US15636278

申请日：2017-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G06F30/394 ,  G06F30/39 ,  G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

公开(公告)号：US20220147668A1

公开(公告)日：2022-05-12

申请号：US17094690

申请日：2020-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicholas Malaya ,  Jakub Kurzak

IPC: G06F30/27 ,  G06F17/18 ,  G06K9/62

Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.

公开(公告)号：US11321241B2

公开(公告)日：2022-05-03

申请号：US17008435

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Michael W. LeBeane

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/0846

Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.

公开(公告)号：US20220130342A1

公开(公告)日：2022-04-28

申请号：US17134770

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ASHISH JAIN ,  DHIRENDRA PARTAP SINGH RANA ,  SAMUEL NAFFZIGER ,  GIA TUNG PHAN ,  BENJAMIN TSIEN

IPC: G09G3/36 ,  G09G3/20 ,  G06F12/0895 ,  G06F12/0811 ,  G06F1/3234

Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

公开(公告)号：US20220129752A1

公开(公告)日：2022-04-28

申请号：US17571045

申请日：2022-01-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sateesh Lagudu ,  Lei Zhang ,  Allen Rush

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for implementing memory bandwidth reduction techniques for low power convolutional neural network inference applications are disclosed. A system includes at least a processing unit and an external memory coupled to the processing unit. The system detects a request to perform a convolution operation on input data from a plurality of channels. Responsive to detecting the request, the system partitions the input data from the plurality of channels into 3D blocks so as to minimize the external memory bandwidth utilization for the convolution operation being performed. Next, the system loads a selected 3D block from external memory into internal memory and then generates convolution output data for the selected 3D block for one or more features. Then, for each feature, the system adds convolution output data together across channels prior to writing the convolution output data to the external memory.

公开(公告)号：US11315883B2

公开(公告)日：2022-04-26

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.