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公开(公告)号：US20250078922A1
公开(公告)日：2025-03-06
申请号：US18241812
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.
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公开(公告)号：US20250076048A1
公开(公告)日：2025-03-06
申请号：US18240955
申请日：2023-08-31
Applicant: STMicroelectronics International N.V.
Inventor： Alessandro MAGNANI , Matteo QUARTIROLI , Alessandro MECCHIA
IPC: G01C19/5712 , G01C25/00
Abstract: A sensor module includes a pattern generator configured to generate a variable frequency self-test signal. The sensor module includes an inertial sensor including a self-test electrode configured to receive the frequency sweep self-test signal. The inertial sensor is configured to generate an analog sensor signal based on the self-test signal. The sensor module includes an analog to digital converter configured to generate a digital sensor signal based on the analog sensor signal and a demodulator including a first input configured to receive the digital sensor signal, a second input configured to receive the self-test signal, and an output configured to output a demodulated signal. The sensor module includes a first low pass filter coupled to the output of the demodulator and configured to generate a baseband signal. The sensor module includes a calibration circuit configured to identify different MEMS characteristics, like resonance frequency, Q-factor, or sensitivity based on the baseband signal.
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公开(公告)号：US20250072787A1
公开(公告)日：2025-03-06
申请号：US18458879
申请日：2023-08-30
Inventor： Diego CARRERA , Carlo GHIGLIONE , Beatrice ROSSI , Pasqualina FRAGNETO , Giacomo BORACCHI
Abstract: A method of operating an inertial sensor module includes receiving a stream of inertial sensor data representing activity of a user of an electronic device and generating a plurality of wavelet sub-bands by performing a wavelet transform on the inertial sensor data. The method includes identifying a wavelet sub-band of highest energy from the plurality of wavelet sub-bands, generating augmented inertial sensor data by combining the wavelet sub-band of highest energy to the inertial sensor data, and identifying a first transition in the activity of the user based on the augmented inertial sensor data.
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公开(公告)号：US20250072131A1
公开(公告)日：2025-02-27
申请号：US18799430
申请日：2024-08-09
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Jean SCHOLLHAMMER
IPC: H01L27/146
Abstract: The present disclosure relates to a method of manufacturing a light sensor comprising a matrix of pixels each associated to a micro-lens having a shift with respect to the pixel. For each axis of a plurality of axes passing by the optical center of the matric, for each pixel on the axis, and for each of a plurality light incident angles, a response value of the pixel is obtained. Based on the response values, for each axis and each pixel on the axis, a first function providing the light incident angle for which the pixel has the best response value is determined. For each axis and each pixel on the axis, a second value of the shift for bringing closer the first function to a target function is determined. The sensor is manufactured using the second values of shift.
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公开(公告)号：US20250069623A1
公开(公告)日：2025-02-27
申请号：US18946503
申请日：2024-11-13
Applicant: STMicroelectronics International N.V.
Inventor： Paolo Pulici , Michele Bartolini , Enrico Sentieri , Enrico Mammei , Matteo Tonelli , Dennis Hogg
IPC: G11B5/60
Abstract: A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.
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Patent Agency Ranking
公开(公告)号：US20250062787A1
公开(公告)日：2025-02-20
申请号：US18792745
申请日：2024-08-02
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Jean-Pierre LAGARDE
Abstract: Apparatuses, systems, and methods for radio frequency communication circuit are provided. For example, a radio frequency communication device includes a clock signal generator configured to deliver a clock signal, based on a time base common to a communication mode and to a standby mode, from a first reference signal and a second reference signal.
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公开(公告)号：US12229253B2
公开(公告)日：2025-02-18
申请号：US17340164
申请日：2021-06-07
Inventor： Asif Rashid Zargar , Gilles Eyzat , Charul Jain
IPC: G06F21/55
Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
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公开(公告)号：US20250055447A1
公开(公告)日：2025-02-13
申请号：US18798124
申请日：2024-08-08
Applicant: STMicroelectronics International N.V.
Inventor： Abdessamed MEKKI , Laurent SIMONY
Abstract: A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.
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公开(公告)号：US20250055376A1
公开(公告)日：2025-02-13
申请号：US18232185
申请日：2023-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Ranajay Mallik , Akshat Jain
IPC: H02M3/335 , H02M1/00 , H02M3/00 , H02M7/5387
Abstract: According to an embodiment, an LLC resonant converter includes a switching bridge having a plurality of power switches. The switching bridge is configured to receive a DC voltage input and generate a square waveform based on a pulse-modulated frequency (PFM) signal at the switching bridge. The LLC resonant converter further includes a resonant tank circuit coupled to the switching bridge. The resonant tank circuit includes a resonant inductor. The resonant tank circuit is excited in response to receiving the square waveform. The PFM signal is adjusted such that an elapsed time between a rising edge of a Drain-Source Voltage of a power switch and a zero-crossing point of current flowing through the resonant inductor falls within a predetermined range corresponding to the resonant tank circuit operating at its resonant frequency.
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公开(公告)号：US20250054528A1
公开(公告)日：2025-02-13
申请号：US18929840
申请日：2024-10-29
Applicant: STMicroelectronics International N.V.
Inventor： Praveen Kumar VERMA , Promod KUMAR , Harsh RAWAT
IPC: G11C8/20 , G11C11/418
Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.
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