METHOD OF TRANSMITTING A PACKET OF DIGITAL DATA OVER A POLY-PHASE POWER LINE AFFECTED BY IMPULSIVE NOISE
    421.
    发明申请
    METHOD OF TRANSMITTING A PACKET OF DIGITAL DATA OVER A POLY-PHASE POWER LINE AFFECTED BY IMPULSIVE NOISE 有权
    通过阴影噪声影响多相电力线数字数据分组的方法

    公开(公告)号:US20110002400A1

    公开(公告)日:2011-01-06

    申请号:US12828684

    申请日:2010-07-01

    CPC classification number: H04B3/542 H04B2203/542 H04B2203/5466

    Abstract: The method transmits a long packet of digital data over a poly-phase power line affected by impulsive noise synchronous with phase voltages. Instead of using very complicated coding schemes, starting from the knowledge of the typical power line scenario, useful information is transmitted where noise synchronous with the main signal is absent. Time-intervals of a known or estimated duration during which the poly-phase power line is affected by impulsive noise are determined, and dummy data during the time-intervals, and useful data during other time-intervals free from impulsive noise, are transmitted.

    Abstract translation: 该方法通过影响与相电压同步的脉冲噪声的多相电力线传输数据数据的长包。 代替使用非常复杂的编码方案,从典型电力线情景的知识开始,传输与主信号同步的噪声不存在的有用信息。 确定多相电力线受脉冲噪声影响的已知或估计的持续时间的时间间隔,并且在时间间隔期间发送伪数据,以及在其它时间间隔内没有冲击噪声的有用数据。

    FAST SWITCHING, OVERSHOOT-FREE, CURRENT SOURCE AND METHOD
    423.
    发明申请
    FAST SWITCHING, OVERSHOOT-FREE, CURRENT SOURCE AND METHOD 有权
    快速切换,免维护,电流源和方法

    公开(公告)号:US20100295476A1

    公开(公告)日:2010-11-25

    申请号:US12727877

    申请日:2010-03-19

    Inventor: Pasquale Franco

    CPC classification number: H05B37/032 G05F1/561 Y10T29/4913

    Abstract: A method and a circuit may have an ability to provide constant currents of a certain set value, the rising and falling edges of which may be shorter than the design minimum on-phase. Essentially, these results may be obtained by keeping an operational amplifier that controls the output power switch in an active state during off-phases of an impulsive drive signal received by the current source circuit in order to maintain the output voltage of the operational amplifier at or just below the voltage to be applied to the control terminal of the output power switch during a successive on-phase of a received drive pulse signal.

    Abstract translation: 方法和电路可以具有提供一定设定值的恒定电流的能力,其上升沿和下降沿可能比设计的最小同相时间短。 本质上,这些结果可以通过将运算放大器保持在由电流源电路接收到的脉冲驱动信号的非相位期间处于激活状态而获得,以便将运算放大器的输出电压保持在或 刚好低于在接收的驱动脉冲信号的连续接通相位期间施加到输出功率开关的控制端子的电压。

    METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES
    424.
    发明申请
    METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES 有权
    使用自适应复位脉冲进行相位变化的多重编程的方法

    公开(公告)号:US20100284212A1

    公开(公告)日:2010-11-11

    申请号:US12780580

    申请日:2010-05-14

    Abstract: A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.

    Abstract translation: 用于编程多电平PCM单元的方法设想:通过施加一个或多个复位脉冲,在PCM单元的存储元件中形成非晶相变材料的非晶区域; 以及通过施加一个或多个设定脉冲,形成所述PCM单元的编程状态的导电路径的大小和与其相关联的输出电量,并通过所述值来控制所述晶体相变材料的导电路径通过所述非晶区域 的复位脉冲和设定脉冲。 形成非晶区域的步骤设想在编程操作期间自适应地和迭代地确定针对PCM单元的电气和/或物理特性优化的复位脉冲的值,特别是确定复位脉冲的最小振幅值, 这允许编程期望的编程状态和输出电量的期望值。

    METHOD AND CIRCUIT FOR AVOIDING HARD SWITCHING IN HALF BRIDGE CONVERTERS
    425.
    发明申请
    METHOD AND CIRCUIT FOR AVOIDING HARD SWITCHING IN HALF BRIDGE CONVERTERS 有权
    避免桥梁转换器硬开关的方法和电路

    公开(公告)号:US20100259951A1

    公开(公告)日:2010-10-14

    申请号:US12421135

    申请日:2009-04-09

    CPC classification number: H02M3/337 H02M2001/0048 Y02B70/1433 Y02B70/1491

    Abstract: A half bridge switching dc-dc converter an input dc voltage to an output dc voltage. The converter includes a switching circuit for receiving the input dc voltage and generating a periodic square wave voltage oscillating from a high value corresponding to the input dc voltage to a low value corresponding to a reference voltage. The periodic square wave voltage oscillates at a main frequency with a main duty cycle equal to about 50% when the converter operates in a steady state. The converter further includes a conversion circuit for providing the output dc voltage from the square wave voltage based on the main frequency and on the main duty cycle. The converter still further comprises a switching control circuit controlling the switching circuit for temporarily varying the main duty cycle during at least one period of the square wave after a power on of the converter.

    Abstract translation: 半桥开关dc-dc转换器将输入直流电压转换为输出直流电压。 该转换器包括用于接收输入直流电压并产生从对应于输入直流电压的高值振荡到对应于参考电压的低值的周期性方波电压的开关电路。 当转换器工作在稳定状态时,周期性方波电压以主频率振荡,主占空比等于约50%。 该转换器还包括一个转换电路,用于根据主频率和主占空比从方波电压提供输出直流电压。 转换器还包括开关控制电路,控制开关电路,用于在转换器通电之后的至少一个方波周期期间暂时改变主占空比。

    DOWN-CONVERTER MIXER
    428.
    发明申请
    DOWN-CONVERTER MIXER 审中-公开
    下变频混频器

    公开(公告)号:US20100164595A1

    公开(公告)日:2010-07-01

    申请号:US12642029

    申请日:2009-12-18

    Inventor: Francesco RADICE

    CPC classification number: H03D7/1433 H03D7/1441 H03D7/1458 H03D7/1491

    Abstract: A down-converter mixer may include a Gilbert cell, two transistor differential pairs, which drive output loads, and transistors defining respective tail generators coupled to common source nodes of the differential pairs. The transistors may receive a radio-frequency signal mixable with a local oscillator signal applied symmetrically between the differential pairs to produce in the loads, a signal deriving from down-converting the radio-frequency signal of an amount given by the frequency of the local oscillator signal. An inductor may be coupled to the common source nodes and which resonates with a capacitive load also coupled to the common source nodes, increases the impedance of such common nodes at the local oscillator signal frequency. The inductor may be in an open loop configuration in the absence of feedback from the mixer, and thus may be active both against noise at radio-frequency and distortion at low frequency.

    Abstract translation: 下变换器混频器可以包括吉尔伯特单元,驱动输出负载的两个晶体管差分对,以及限定耦合到差分对的公共源节点的相应尾部发生器的晶体管。 晶体管可以接收可与在差分对之间对称地施加的本地振荡器信号混合的射频信号,以在负载中产生从由本地振荡器的频率给出的量的频率信号下变频的信号 信号。 电感器可以耦合到公共源节点并且与也耦合到公共源节点的电容性负载谐振,增加了本地振荡器信号频率处的这些公共节点的阻抗。 在没有来自混频器的反馈的情况下,电感器可以是开环配置,并且因此可以在低频下的无线电频率和失真的情况下都有效。

    ELECTRONIC AMPLIFICATION DEVICE WITH CURRENT MIRROR FOR INTEGRATED POWER AMPLIFIERS
    430.
    发明申请
    ELECTRONIC AMPLIFICATION DEVICE WITH CURRENT MIRROR FOR INTEGRATED POWER AMPLIFIERS 有权
    具有集成功率放大器电流镜的电子放大器件

    公开(公告)号:US20100159853A1

    公开(公告)日:2010-06-24

    申请号:US12643373

    申请日:2009-12-21

    Abstract: The disclosure relates to an electronic differential amplification device integrated on a semiconductor chip. The device may include first and second transistors having respective source terminals connected to a first potential, and drain terminals to receive a first differential current signal. The device may include third and fourth transistors having respective source terminals connected to the first potential, and drain terminals to provide a second differential current signal to a load obtained by amplifying the first signal. The third and fourth transistors may have a respective gate terminal connected to the drain terminal of the first and the second transistors, respectively, in order to form current mirrors with the latter. The device is characterized in that the first and second transistors may have the respective gate terminals electrically connected to a common terminal, and at least one first and at least one second resistive elements are connected between the common terminal and the drain terminals of the first and the second transistors, respectively.

    Abstract translation: 本公开涉及集成在半导体芯片上的电子差分放大装置。 器件可以包括具有连接到第一电位的相应源极端子的第一和第二晶体管以及用于接收第一差分电流信号的漏极端子。 器件可以包括具有连接到第一电位的相应源极端子的第三和第四晶体管,以及用于通过放大第一信号而获得的负载来提供第二差分电流信号的漏极端子。 第三和第四晶体管可以具有相应的栅极端子,分别连接到第一和第二晶体管的漏极端子,以便与后者形成电流镜。 该器件的特征在于,第一和第二晶体管可以具有电连接到公共端子的相应的栅极端子,并且至少一个第一和至少一个第二电阻元件连接在第一和第二晶体管的公共端子和漏极端子之间, 第二晶体管。

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