Radio-frequency transceiver device, corresponding system and method

    公开(公告)号:US10924194B2

    公开(公告)日:2021-02-16

    申请号:US16394633

    申请日:2019-04-25

    Abstract: A radio-frequency transceiver device includes a transmission circuit generating a transmission signal at a transmission pad connected to a transmission antenna by modulating a radio frequency signal as a function of a control signal. First and second reception circuits receive first and second signals at first and second reception pads connected to first and second reception antennas. The received first and second signals are demodulated via the radio frequency signal to generate first and second demodulated reception signals. A control circuit operates during a reception test phase to generate only the control signal in order to test, as a function of the first and second demodulated reception signals, whether the received first signal corresponds to the received second signal. A reception error signal indicating a reception error is generated when the test indicates that the received first and second reception signals do not correspond.

    Control circuit for power switch
    442.
    发明授权

    公开(公告)号:US10917087B2

    公开(公告)日:2021-02-09

    申请号:US16719053

    申请日:2019-12-18

    Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

    High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor

    公开(公告)号:US10916622B2

    公开(公告)日:2021-02-09

    申请号:US16144168

    申请日:2018-09-27

    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

    Capacitive pressure sensor for monitoring construction structures, particularly made of concrete

    公开(公告)号:US10914647B2

    公开(公告)日:2021-02-09

    申请号:US16023918

    申请日:2018-06-29

    Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.

    Power semiconductor device with a double island surface mount package

    公开(公告)号:US10910302B2

    公开(公告)日:2021-02-02

    申请号:US16385928

    申请日:2019-04-16

    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

    Switched-resistor sensor bridge, corresponding system and method

    公开(公告)号:US10900849B2

    公开(公告)日:2021-01-26

    申请号:US16512912

    申请日:2019-07-16

    Abstract: A sensing bridge includes first and second branches in parallel, the first branch including a first resistor in series with a first switch, the second branch including a second resistor in series with a second switch. Resistances of the resistors vary with a sensed physical variable. The branches switch between first and second phases, with the first switch closed and the second switch open during the first phase, and the first switch open and the second switch closed during the second phase. A reference block generates a control signal from the resistance of the variable resistors during the first and second phases. An oscillator generates an oscillating signal during the first and second phases from the variable sense current during the first and second phases. Processing circuitry determines a value of the sensed physical value from an algebraic combination of the oscillating signal during the first and second phases.

    HALF-BRIDGE DRIVER CIRCUIT
    449.
    发明申请

    公开(公告)号:US20210013808A1

    公开(公告)日:2021-01-14

    申请号:US16924410

    申请日:2020-07-09

    Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.

    PHASE CHANGE MEMORY WITH SUPPLY VOLTAGE REGULATION CIRCUIT

    公开(公告)号:US20210012836A1

    公开(公告)日:2021-01-14

    申请号:US16924760

    申请日:2020-07-09

    Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.

Patent Agency Ranking