公开(公告)号：US20240403050A1

公开(公告)日：2024-12-05

申请号：US18509121

申请日：2023-11-14

Applicant: Arm Limited

Inventor： Joshua Randall ,  Siying Feng

IPC: G06F9/30

Abstract: The present disclosure relates generally to integrated circuits and relates more particularly to vector comparison and/or population count operations, such as for vector sorting, merging, and/or intersection.

公开(公告)号：US12159223B2

公开(公告)日：2024-12-03

申请号：US17084249

申请日：2020-10-29

Applicant: Arm Limited

Inventor： Davide Marani ,  Erik Persson ,  Viet-Hoa Do ,  Dan Staffan Henrik Johansson

IPC: G06N3/08 ,  G06F7/76 ,  G06F17/16 ,  G06N3/063

Abstract: A method of processing image data of a neural network is performed by a data processing apparatus and comprises writing a first tensor to first storage of the data processing apparatus using a row stride, wherein the first tensor comprises at least one data group, the at least one data group comprising a plurality of data samples and having height, width, and depth dimensions [h, w, c]. The method further comprises transforming the first tensor into a second tensor using a first stride such that the second tensor is a column tensor comprising a plurality of rows, and writing the second tensor to second storage using a second stride that is related to a multiple of the first stride, δn, such that the second stride covers a first set of memory elements in the second storage into which data samples of a first row of the second tensor are stored and a second set of memory elements into which no data samples from the second tensor are stored.

公开(公告)号：US12148697B2

公开(公告)日：2024-11-19

申请号：US17125704

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Jean-Luc Pelloie

IPC: H01L23/528 ,  G06F30/3953 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.

公开(公告)号：US20240378084A1

公开(公告)日：2024-11-14

申请号：US18316125

申请日：2023-05-11

Applicant: Arm Limited

Inventor： Elliot Maurice Simon Rosemarine ,  Alexander Eugene Chalfin ,  Ozgur Tasdizen ,  Tord Kvestad Øygard

IPC: G06F9/50

Abstract: According to the present techniques there is provided a method of operating a data processor unit to generate processing tasks: the data processor unit comprising: a control circuit to receive, from a host processor unit, a request for the data processor unit to perform a processing job; an iterator unit to process the request and generate a workload comprising one or more tasks for the requested job; one or more execution units to perform the one or more tasks; storage to store system information indicative of a status of at least one component of the data processor unit; the method comprising: receiving, at the control circuit, a first request to perform a first processing job; processing, at the iterator unit, the first request and generating a workload comprising one or more tasks for the first processing job based on or in response to the system information in storage, wherein at least one characteristic of the workload is dependent on the system information.

公开(公告)号：US20240371074A1

公开(公告)日：2024-11-07

申请号：US18602583

申请日：2024-03-12

Applicant: Arm Limited

Inventor： Richard Edward Bruce ,  Jakob Axel Fries

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray intersects a volume represented by a node of a ray tracing acceleration data structure that is associated with a bounding volume primitive, the ray is not tested against the bounding volume primitive to determine whether the ray intersects the bounding volume primitive.

公开(公告)号：US12131155B2

公开(公告)日：2024-10-29

申请号：US17597134

申请日：2020-03-25

Applicant: ARM LIMITED ,  THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE

Inventor： Peng Sun ,  Timothy Martin Jones ,  Giacomo Gabrielli

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3004 ,  G06F9/3555 ,  G06F9/3842

Abstract: An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.

公开(公告)号：US12124711B2

公开(公告)日：2024-10-22

申请号：US17944553

申请日：2022-09-14

Applicant: Arm Limited

Inventor： Roberto Avanzi

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0659 ,  G06F3/0673

Abstract: Apparatus, methods, and software for protecting a plurality of memory locations are disclosed. Logical addresses are translated into physical addresses in dependence on one of a first translation function and a second translation function. A transitional logical address and an associated transitional value are locally held in circuitry which applies the translation functions. A remapping of first to second translation function usage is performed by determining a new transitional physical address by applying the second translation function to the transitional logical address; determining a new transitional logical address by applying an inverse of the first translation function to the new transitional physical address; retrieving a new transitional value using the new transitional physical address; storing the old transitional value to the memory location indicated by the new transitional physical address; and locally storing the new transitional value. This remapping can be interleaved with normal memory accesses.

公开(公告)号：US20240346155A1

公开(公告)日：2024-10-17

申请号：US18299216

申请日：2023-04-12

Applicant: Arm Limited

Inventor： Roberto AVANZI ,  Andreas Lars SANDBERG ,  Ionut Alexandru MIHALCEA ,  David Helmut SCHALL ,  Alexander KLIMOV

IPC: G06F21/60 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F21/78

Abstract: Apparatuses and methods for memory protection are disclosed. A memory protection apparatus is interposed between a system cache and a memory system. The apparatus comprises encryption circuitry, which encrypts data item in dependence on encryption metadata and decrypts encrypted data items in dependence on the encryption metadata. In response to a change in a metadata item of the encryption metadata, when no cached copy of an affected data item is currently in the system cache, the affected data item is retrieved from the memory system, re-encrypted using the updated metadata item and returned to the memory system. When there is a cached copy, in dependence on update control data, the copy is retrieved from the system cache, encrypted using the updated metadata item and written out to the memory system.

公开(公告)号：US12118101B2

公开(公告)日：2024-10-15

申请号：US17903267

申请日：2022-09-06

Applicant: Arm Limited

Inventor： Brendan James Moran ,  Adrian Laurence Shaw ,  Andreas Lars Sandberg

IPC: G06F21/60 ,  G06F21/53

CPC classification number: G06F21/604 ,  G06F21/53

Abstract: An apparatus and method are described for providing a trusted execution environment. The apparatus comprises processing circuitry to execute program code, and interrupt controller circuitry, responsive to receipt of one or more interrupt requests, to select a given interrupt request from amongst the one or more interrupt requests, and to issue an interrupt signal to the processing circuitry identifying a given interrupt service routine providing program code to be executed by the processing circuitry to service the given interrupt request. The interrupt controller circuitry is responsive to the given interrupt request being a trusted execution environment (TEE) interrupt request, to issue the interrupt signal to identify as the given interrupt service routine a TEE interrupt service routine, and to inhibit issuance of any further interrupt signal until the TEE interrupt service routine has been executed by the processing circuitry. The interrupt controller circuitry comprises code protection circuitry to inhibit unauthorised modification of the TEE interrupt service routine, and data protection circuitry to inhibit unauthorised access to confidential data processed by the TEE interrupt service routine.

公开(公告)号：US20240320332A1

公开(公告)日：2024-09-26

申请号：US18186454

申请日：2023-03-20

Applicant: Arm Limited

Inventor： Michael BARTLING

IPC: G06F21/56 ,  G06F21/53

CPC classification number: G06F21/563 ,  G06F21/53

Abstract: A live attack shadow replay can be performed at a shadow replay box that receives a snapshot of a computer program executed by an operating system of a device; mirrors an execution environment of the snapshot; determines a typical execution of the computer program comprising a first set of variables; performs a static analysis on the snapshot of the computer program to determine a second set of variables; determines a divergence between the first set of variables and the second set of variables; marks variables of the second set of variables that are associated with the divergence; replays a portion of the computer program corresponding to at least the snapshot; and monitors the marked variables of the second set of variables during the replaying of the portion of the computer program.