公开(公告)号：US06426949B1

公开(公告)日：2002-07-30

申请号：US09098357

申请日：1998-06-17

Applicant: Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B7216

CPC classification number: H04B1/707 ,  H04B1/7115 ,  H04B2201/70701

Abstract: A signal reception apparatus for DS-CDMA communication system having a complex matched filter for despreading a received signal into I- and Q-components Di and Dq of despread signal. Dj and Dq are input to a path selection portion 13 for extracting a phase error in a pilot symbol block of the despread signal. A phase compensation signal is calculated according to the phase error in the portion 13. An information symbol is compensated according to the phase compensation signal. An electrical power is calculated from an average of the phase compensation signal of several slots for selecting paths to be received. The selected paths are combined with phase synchronized by a rake combiner 14.

Abstract translation: 一种具有复数匹配滤波器的DS-CDMA通信系统的信号接收装置，用于将接收信号解扩展成解扩信号的I和Q分量Di和Dq。 Dj和Dq被输入到路径选择部分13，用于提取去扩展信号的导频符号块中的相位误差。 根据部分13中的相位误差来计算相位补偿信号。根据相位补偿信号补偿信息符号。 从用于选择要接收的路径的几个时隙的相位补偿信号的平均值计算电功率。 所选择的路径与由耙式组合器14相位同步的组合。

公开(公告)号：US06388583B1

公开(公告)日：2002-05-14

申请号：US09588613

申请日：2000-06-06

Applicant: Biqi Long ,  Changming Zhou

Inventor： Biqi Long ,  Changming Zhou

IPC: H03M700

CPC classification number: H04J13/10

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

Abstract translation: 本发明提供了一种方法和电路，用于产生能够在较短的等待时间内在反向信道上发送长码的代码。 该方法涉及对应于序列M或长码周期的开始之间的移位量，以及每个定时到多个掩蔽数据的组合; 确定用于响应于在尽可能快的时间点的传输请求开始生成长码的定时的掩蔽数据的组合; 以及根据掩蔽数据移动矢量的初始值。

公开(公告)号：US6038250A

公开(公告)日：2000-03-14

申请号：US3509

申请日：1998-01-06

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

IPC: H04B1/707 ,  H04B1/7075 ,  H04B7/26 ,  H04W56/00 ,  H04W76/02 ,  H04B7/216

CPC classification number: H04B1/7077 ,  H04B1/7083 ,  H04B1/70735 ,  H04B1/70751 ,  H04B2201/70702

Abstract: Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.

Abstract translation: 使用初始同步方法和用于DS-CDMA基站间异步蜂窝系统的接收机以高速搜索小区。 基带接收信号被输入到匹配滤波器，并与从扩展码发生器提供的扩展码相关。 信号电力计算器计算匹配滤波器的相关输出的功率，并将结果输出到长码同步定时确定器，阈值计算器和长码标识符。 在初始小区搜索期间，扩频码发生器输出每个基站的控制信道共同的短码＃0。 在确定了长代码同步定时之后，构成从每个基站唯一的长码#i合成的合成扩展码序列的一部分的N个码片的每个片段和短码＃0 顺序更换并输出。

公开(公告)号：US5959875A

公开(公告)日：1999-09-28

申请号：US812650

申请日：1997-03-07

Applicant: Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

Inventor： Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

IPC: G06G7/19

CPC classification number: G06G7/1921

Abstract: A signal characterizer for performing functional transformations such as Fast Fourier Transforms (FFTs), which converts an input serial analog signal into a plurality of parallel discrete signals using an analog-type serial-to-parallel converter. The discrete signals are then supplied to the input terminals of butterfly operation circuits to process the parallel discrete signals into a plurality of transformed signals. A switch supplies the transformed signals to a serial signal output terminal. The switch is controlled by a controller so that the input signal sequence is converted to a serial signal sequence according to a predetermined order.

Abstract translation: 一种用于执行诸如快速傅立叶变换（FFT）的功能变换的信号表征器，其使用模拟型串并转换器将输入的串行模拟信号转换为多个并行离散信号。 然后将离散信号提供给蝶形运算电路的输入端，以将并行离散信号处理成多个变换信号。 开关将变换的信号提供给串行信号输出端子。 开关由控制器控制，使得输入信号序列根据预定顺序被转换成串行信号序列。

公开(公告)号：US5887024A

公开(公告)日：1999-03-23

申请号：US780145

申请日：1996-12-26

Applicant: Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

Inventor： Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

IPC: H03H11/04 ,  H03H17/02 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC classification number: H03H11/04 ,  H03H17/02

Abstract: The present invention provides a matched filter which can refresh an entire while keeping the speed of a calculation comparable to a small sized circuit. The first and second addition circuits of a matched filter of the present invention are classified into a plurality of groups, the first and second auxiliary adders replace functions for the groups of the first and second adders respectively. The outputs of the first and second adders are then inputted to the first and second subtractors, respectively, and the refreshing means appropriately refreshes the groups replaced by the first and second auxiliary adders. Further, the present invention decreases the number of auxiliary sapling and holding circuits to be used, and decides the refreshing intervals by considering the change of the voltage caused by leakage and other permissible errors of output voltage.

Abstract translation: 本发明提供了一种匹配滤波器，其可以保持与小尺寸电路相当的计算速度的整体刷新。 本发明的匹配滤波器的第一和第二加法电路分为多个组，第一和第二辅助加法器分别代替第一和第二加法器的组的功能。 然后，第一和第二加法器的输出分别输入到第一和第二减法器，并且刷新装置适当地刷新由第一和第二辅助加法器替换的组。 此外，本发明减少了要使用的辅助树苗和保持电路的数量，并且通过考虑由漏电引起的电压的变化和输出电压的其他允许误差来决定刷新间隔。

公开(公告)号：US5841315A

公开(公告)日：1998-11-24

申请号：US686958

申请日：1996-07-26

Applicant: Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H03M1/66 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H03M3/02 ,  H03K5/00 ,  G11C27/02 ,  H03K12/00

CPC classification number: H04B1/7093 ,  H03H11/04 ,  H03H17/0254 ,  H04B1/7117

Abstract: An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

Abstract translation: 本发明的目的是提供一种尺寸小且消耗低功率的匹配滤波电路。 注意扩展码是1位数据串，输入信号被采样并保持为沿着时间序列的模拟信号，分为“1”和“-1”，分类信号通过电容耦合并联 在根据本发明的匹配滤波器电路中。

公开(公告)号：US5740096A

公开(公告)日：1998-04-14

申请号：US708986

申请日：1996-09-06

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC: H03M1/12 ,  H03H11/04 ,  H03H17/00 ,  H03H17/02 ,  H04B1/69 ,  H04J13/00 ,  G06G7/02

CPC classification number: H03H17/0254 ,  H03H11/04 ,  H04B1/7093

Abstract: The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.