公开(公告)号：US06781191B2

公开(公告)日：2004-08-24

申请号：US10621431

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L29788

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06770520B2

公开(公告)日：2004-08-03

申请号：US10436800

申请日：2003-05-13

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21337

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。 导电层的表面被图案化的硬掩模层覆盖以形成栅极。 使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。 导电层被氧化以在导电层的表面上形成氧化物层。 使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。

公开(公告)号：US06734066B2

公开(公告)日：2004-05-11

申请号：US10307704

申请日：2002-12-02

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L21336

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US06562673B2

公开(公告)日：2003-05-13

申请号：US09948530

申请日：2001-09-07

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L218238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating a memory cell of self-aligned split gate flash memory first provides a substrate having an active area. A first gate insulating layer, a conductive layer and a buffer layer are formed within the active area. A portion of the buffer layer is removed to form a first opening. A buffer spacer is formed on the side walls of the first opening. A portion of the conductive layer and first gate insulating layer under the first opening are removed to form a second opening. The contact spacers, the source region and the contact plug are formed in the second opening in sequence. After the buffer spacers are removed, a third opening is formed. The bottom surface of the third opening and the top surface of the contact plug are oxidized to form the oxide layers. Another buffer spacers fill the third opening. The remaining buffer layer is removed to form the fourth opening. The conductive layer under the bottom of the fourth opening is removed, except the portion under the oxide layer, to form the floating gates. After the formation of a second gate insulating layer, the control gates and the control gate spacers are formed in sequence.

公开(公告)号：US06518153B1

公开(公告)日：2003-02-11

申请号：US09562911

申请日：2000-05-02

Applicant: Chi-hui Lin ,  Chung Lin Huang

Inventor： Chi-hui Lin ,  Chung Lin Huang

IPC: H01L913205

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L27/10873 ,  H01L29/4941

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract translation: 提供一种制造嵌入式DRAM器件的方法，其中集成了满足高性能逻辑电路要求的低片电阻的栅电极。 半导体衬底上的栅电极包括栅极氧化膜，多晶硅膜，金属，轻掺杂扩散层，二氧化硅间隔物和源极/漏极扩散层。 将金属种植在开口中，其中用于在多晶硅膜顶部占据的封盖氮化硅。

公开(公告)号：US06511881B1

公开(公告)日：2003-01-28

申请号：US10191722

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for fabricating split gate flash memory cell. The method includes sequentially forming conductive layers and insulating layers on a semiconductor substrate, followed by forming a first opening in the conductive layers and the insulating layers. Next, a shallow trench isolation is defined in the first opening and an insulating layer is defined simultaneously in the active area within the shallow trench isolation to form a first gate isolation layer. Then, a conductive sidewall layer is formed on the sidewalls of the first gate insulating layer. The first gate insulating layer and the conductive sidewall layer are used as a hard mask to remove the conductive layer not covered by the hard mask, thus forming a floating gate comprised of the conductive sidewall layer and the conductive layer underneath. A second gate insulating layer, control gate and source/drain are then formed conventionally.

Abstract translation: 一种用于制造分流栅闪存单元的方法。 该方法包括在半导体衬底上依次形成导电层和绝缘层，随后在导电层和绝缘层中形成第一开口。 接下来，在第一开口中限定浅沟槽隔离，并且在浅沟槽隔离中的有源区域中同时限定绝缘层，以形成第一栅极隔离层。 然后，在第一栅极绝缘层的侧壁上形成导电侧壁层。 第一栅绝缘层和导电侧壁层用作硬掩模以去除未被硬掩模覆盖的导电层，从而形成由导电侧壁层和下面的导电层组成的浮栅。 然后通常形成第二栅极绝缘层，控制栅极和源极/漏极。