公开(公告)号：US06510094B2

公开(公告)日：2003-01-21

申请号：US09940909

申请日：2001-08-28

Applicant: Min-Chul Chung ,  Chang-Rae Kim ,  Sang-Jib Han ,  Jong-Yul Park

Inventor： Min-Chul Chung ,  Chang-Rae Kim ,  Sang-Jib Han ,  Jong-Yul Park

IPC: G11C700

CPC classification number: G11C11/4085 ,  G11C11/406

Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.

Abstract translation: 公开了一种半导体存储器件，包括多个子字线驱动器，其布置在位线方向上的所有存储单元阵列块上，并分别由两个存储单元阵列块共享;多个块读出放大器，布置在所有存储单元 并且分别由两个存储单元阵列块共享的多个电路块，分别布置在容纳子字线驱动器和块读出放大器的区域的连接区域; 所述连接区域包括适于驱动块读出放大器的一个或多个LA驱动器，适于产生用于控制子字线驱动器的驱动控制信号的一个或多个PXiD电路以及适于选择性地使LA驱动器响应的一个或多个BSYD电路 传输块控制信号; 以及多个块控制单元，适于通过组合列和行块地址解码信号并且同时使用块控制信号激活两个或更多个BSYD电路来生成上部和下部块控制信号。

公开(公告)号：US6160742A

公开(公告)日：2000-12-12

申请号：US353106

申请日：1999-07-14

Applicant: Min-Chul Chung ,  Kyeong-Rae Kim

Inventor： Min-Chul Chung ,  Kyeong-Rae Kim

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C16/02 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1039

Abstract: The semiconductor memory device includes a memory cell array, sense amplifying means for generating a sense output signal pair, and a data output buffer for providing the sense output signal pair. The data output buffer includes a level shifter for generating a first data output signal pair by shifting the level of the sense output signal pair responsive to the output buffer enable signal. A register inverts and latches the first data output signal pair, generating a second data output signal pair. A first transmission and latch means transmits and latches the second data output signal pair generating a third data output signal pair responsive to a first control signal. A second transmission and latch means transmits and latches the second data output signal pair generating a fourth data output signal pair responsive to a second control signal. A first inverter generates a fifth data output signal pair by inverting the third data output signal pair responsive to a first data output control signal. A second inverter generates the fifth data output signal pair by inverting the fourth data output signal pair responsive to a second data output control signal. A first latch generates a sixth data output signal pair by latching the fifth data output signal pair. A logical multiplication means manipulates the sixth data output signal pair responsive to an output enable signal.

Abstract translation: 半导体存储器件包括存储单元阵列，用于产生感测输出信号对的读出放大装置，以及用于提供感测输出信号对的数据输出缓冲器。 数据输出缓冲器包括电平移位器，用于通过根据输出缓冲器使能信号移位感测输出信号对的电平来产生第一数据输出信号对。 A寄存器反转并锁存第一数据输出信号对，产生第二数据输出信号对。 第一传输和锁存装置响应于第一控制信号发送和锁存产生第三数据输出信号对的第二数据输出信号对。 第二传输和锁存装置响应于第二控制信号发送和锁存产生第四数据输出信号对的第二数据输出信号对。 响应于第一数据输出控制信号，第一反相器通过使第三数据输出信号对反相来产生第五数据输出信号对。 第二反相器响应于第二数据输出控制信号，通过使第四数据输出信号对反相来产生第五数据输出信号对。 第一锁存器通过锁存第五数据输出信号对来产生第六数据输出信号对。 逻辑乘法装置响应于输出使能信号来操纵第六数据输出信号对。

公开(公告)号：US6064609A

公开(公告)日：2000-05-16

申请号：US373447

申请日：1999-08-12

Applicant: Chul-Min Jung ,  Min-Chul Chung

Inventor： Chul-Min Jung ,  Min-Chul Chung

IPC: G11C29/04 ,  G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C29/781

Abstract: Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals. A second decoding means decodes the manipulated versions of the true and complement column address signals and generates third and fourth true decoded pulse signals and third and fourth complement decoded pulse signals. A sense amplification control signal generating means produces the sense amplification control signal responsive to the first, second, third, and fourth true decoded pulse signals and the first, second, third, and fourth complement decoded pulse signals. A row select signal generating means produces the row select signal responsive to first, second, third, and fourth true decoded pulse signals. The above-described redundancy controller improves the redundancy speed.

Abstract translation: 公开了一种包括冗余控制器的半导体存储器件。 冗余控制器使用传递门逻辑，动态反相器电路和真/补码解码器方案构成。 冗余控制器包括分别对应于第一和第二冗余列的第一和第二冗余使能电路。 第一和第二保险丝盒分别耦合到第一和第二冗余使能电路。 第一和第二保险丝盒各自包括对应于列地址信号的熔丝盒电路和熔丝元件。 每个保险丝盒电路接收相应的一对真和补列列地址信号，并响应于熔丝元件操纵真和补列列地址信号。 第一解码装置对真和补列列地址信号的操纵版本进行​​解码，并产生第一和第二真解码脉冲信号以及第一和第二补码解码脉冲信号。 第二解码装置解码真和补列列地址信号的操纵版本，并产生第三和第四真实解码脉冲信号以及第三和第四补码解码脉冲信号。 感测放大控制信号产生装置响应于第一，第二，第三和第四真实解码脉冲信号以及第一，第二，第三和第四补码解码脉冲信号产生感测放大控制信号。 行选择信号发生装置响应于第一，第二，第三和第四真实解码脉冲信号产生行选择信号。 上述冗余控制器提高冗余速度。

公开(公告)号：US3752479A

公开(公告)日：1973-08-14

申请号：US3752479D

申请日：1971-06-10

Applicant: KWANG CHUL CHUNG

Inventor： KWANG CHUL CHUNG

IPC: A63B67/18

CPC classification number: A63B67/18 ,  A63B67/187

Abstract: A shuttlecock or butterfly is provided with an arrangement in which gliding feathers are readily arrayed or rearrayed, attached onto or detached from so as the shuttlecock or butterfly itself be adjusted in its flying range and speed. The arrangement comprises a plurality of pits formed along the upper brim of the bottom cup portion of the basket-like main hopper body, a riblike skirt portion, a plurality of vertical frames and a plurality of knob heads formed on the top of the vertical frames, protruding upwardly from the upper end of the skirt portion. The feathers are secured onto along the inner surface of the vertical frames with the foot portion of the quill inserted in the pits formed along the upper brim of the bottom cup portion and the upper portion of the quill at the middle of the feather tied onto the knob heads formed on the top of the vertical frames by such fastening means as string, wire or adhesive tape.

Abstract translation: 羽毛球或蝴蝶提供有一种布置，其中滑翔羽毛容易排列或重新布置，附接到或分离，因为羽毛球或蝴蝶本身被调节其飞行范围和速度。 该装置包括沿着篮状主料斗主体的底杯部分的上边缘形成的多个凹坑，肋状裙部，多个垂直框架和形成在该顶部的顶部上的多个旋钮头 垂直框架，从裙部的上端向上突出。 羽毛被固定在垂直框架的内表面上，其中羽毛笔的脚部插入沿着底部杯部分的上边缘形成的凹坑中，羽毛中间的羽毛笔的上部被捆扎在 旋钮头通过诸如绳，线或胶带的紧固装置形成在垂直框架的顶部上。

公开(公告)号：US20210348803A1

公开(公告)日：2021-11-11

申请号：US17277671

申请日：2019-09-10

Applicant: Yeon Chul CHUNG

Inventor： Yeon Chul CHUNG

IPC: F24H1/10 ,  F28F1/42 ,  F24D3/02 ,  F24D3/08 ,  H05B1/02

Abstract: According to the present invention, disclosed is a pipe fluid heat exchange flat pipe, which has a cross section having a width direction size that is larger than the size in the height direction thereof, extends in a longitudinal direction, and has a plurality of flat parts and curved parts that are alternately formed, wherein a plurality of lower guides protruding from the inner lower surface of the flat pipe toward the upper side thereof and upper guides protruding from the inner upper surface of the flat pipe toward the lower side thereof are alternately provided in the width direction of the flat pipe, and either the lower guide or the upper guide has an overlapping part overlapped with the other from either of the adjacent lower guide or upper guide in the height direction of the flat pipe.

公开(公告)号：USD761165S1

公开(公告)日：2016-07-12

申请号：US29517292

申请日：2015-02-11

Applicant: Jae Chul Chung

Designer： Jae Chul Chung

公开(公告)号：USD760629S1

公开(公告)日：2016-07-05

申请号：US29517276

申请日：2015-02-11

Applicant: Jae Chul Chung

Designer： Jae Chul Chung

公开(公告)号：USD759544S1

公开(公告)日：2016-06-21

申请号：US29517264

申请日：2015-02-11

Applicant: Jae Chul Chung

Designer： Jae Chul Chung

公开(公告)号：US08331489B2

公开(公告)日：2012-12-11

申请号：US13242490

申请日：2011-09-23

Applicant: Bruno Clerckx ,  Yongxing Zhou ,  Goo Chul Chung

Inventor： Bruno Clerckx ,  Yongxing Zhou ,  Goo Chul Chung

IPC: H04L27/04

CPC classification number: H04L25/03904 ,  H04B7/0413 ,  H04B7/0456 ,  H04B7/0469 ,  H04B7/10 ,  H04L25/0391

Abstract: A method of generating a codebook for a multiple-input multiple-output (MIMO) system is provided. The codebook generation method includes: assigning a single-polarized precoding matrix to diagonal blocks among a plurality of blocks arranged in a block diagonal format in which a number of diagonal blocks corresponds to a number of polarization directions of transmitting antennas; and assigning a zero matrix to remaining blocks excluding the diagonal blocks.

Abstract translation: 提供了一种生成用于多输入多输出（MIMO）系统的码本的方法。 码本生成方法包括：将单偏振预编码矩阵分配给以对角线格式布置的多个块中的对角块，其中多个对角块对应于发射天线的极化方向的数量; 并将零矩阵分配给除对角块之外的剩余块。

公开(公告)号：US20120243709A1

公开(公告)日：2012-09-27

申请号：US13493395

申请日：2012-06-11

Applicant: Chul CHUNG

Inventor： Chul CHUNG

IPC: H03G5/00

CPC classification number: H04N5/775 ,  G06F17/30743 ,  H04L12/2803 ,  H04L12/2838 ,  H04L2012/2849 ,  H04N5/781 ,  H04N5/85 ,  H04N9/8042 ,  H04N21/40 ,  H04R3/04 ,  H04R3/14

Abstract: Integrated processing of audio/video signals can eliminate unnecessary signal processors and converters without losing the functionality of typical home entertainment system components. The integrated system includes a main player that captures and processes signals digitally, a dummy display, and a dummy speaker. The dummy display may only have a display panel and a panel driver. The dummy speaker may only have a driving unit and no crossover logic. The main player may have a PC architecture and process all signals digitally for outputting signals tailored for the display device and the individual driving units of the dummy speaker. The integrated system may also provide dynamic signal adjustments based on the surrounding environment. The main player may include a storage device and can process media content stored therein to produce supplemental information to provide an optimal audiovisual experience. This supplemental information can be shared among users over a network connection.

Abstract translation: 音频/视频信号的集成处理可以消除不必要的信号处理器和转换器，而不会失去典型家庭娱乐系统组件的功能。 集成系统包括以数字方式捕获和处理信号的主播放器，虚拟显示器和虚拟扬声器。 虚拟显示器可以仅具有显示面板和面板驱动器。 虚拟扬声器可以仅具有驱动单元并且不具有交叉逻辑。 主播放器可以具有PC架构并且以数字方式处理所有信号，以输出针对显示装置和虚拟扬声器的各个驱动单元量身定制的信号。 集成系统还可以基于周围环境提供动态信号调整。 主播放器可以包括存储设备并且可以处理存储在其中的媒体内容以产生补充信息以提供最佳视听体验。 该补充信息可以通过网络连接在用户之间共享。