公开(公告)号：US07414911B2

公开(公告)日：2008-08-19

申请号：US11704089

申请日：2007-02-08

Applicant: Hyun-su Choi ,  Kyeong-rae Kim

Inventor： Hyun-su Choi ,  Kyeong-rae Kim

IPC: G11C5/14

CPC classification number: G11C7/22 ,  G11C7/20 ,  G11C2207/2227

Abstract: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

Abstract translation: 存储器件的唤醒电路使用级联链结构，其中位线被分成多个块，并且如果确定一个块的位线已经经历了基于位的唤醒操作 线路电压反馈到块中，在随后的块上执行唤醒操作。 因此，可以改变唤醒延迟，因此可以控制峰值电流，从而降低总体系统功率噪声。

公开(公告)号：US20050286322A1

公开(公告)日：2005-12-29

申请号：US11103047

申请日：2005-04-11

Applicant: Hyun-su Choi ,  Kyeong-rae Kim

Inventor： Hyun-su Choi ,  Kyeong-rae Kim

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/20 ,  G11C2207/2227

Abstract: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

Abstract translation: 存储器件的唤醒电路使用级联链结构，其中位线被分成多个块，并且如果确定一个块的位线已经经历了基于位的唤醒操作 线路电压反馈到块中，在随后的块上执行唤醒操作。 因此，可以改变唤醒延迟，因此可以控制峰值电流，从而降低总体系统功率噪声。

公开(公告)号：US5761132A

公开(公告)日：1998-06-02

申请号：US725641

申请日：1996-10-15

Applicant: Kyeong-Rae Kim

Inventor： Kyeong-Rae Kim

IPC: G11C17/00 ,  G11C7/10 ,  G11C16/06 ,  G11C17/18 ,  G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/103

Abstract: Integrated circuit memory devices with latch-free page buffers therein include a page buffer for electrically coupling a bit line from an array of memory cells to a buffer output. The page buffers generate a first logic state at an output thereof when the bit line is at a first logic potential and a high-impedance logic state when the bit line is at a second logic potential, during a memory read operation. An output buffer is also provided for converting the high-impedance state and the first logic state generated by the page buffer to respective opposite logic states (e.g, logic 1 and logic 0). The bit line data is used to directly trigger the appropriate state of the page buffer output by coupling a gate of an insulated-gate isolation transistor to the bit line data and then reading the source of the isolation transistor as the page buffer output.

Abstract translation: 具有无闩锁页缓冲器的集成电路存储器件包括用于将位线从存储器单元阵列电耦合到缓冲器输出的页缓冲器。 在存储器读取操作期间，当位线处于第一逻辑电位和位线处于第二逻辑电位时的高阻抗逻辑状态下，页缓冲器在其输出处产生第一逻辑状态。 还提供输出缓冲器，用于将由页缓冲器产生的高阻抗状态和第一逻辑状态转换为相应的逻辑状态（例如，逻辑1和逻辑0）。 位线数据用于通过将绝缘栅隔离晶体管的栅极耦合到位线数据，然后将隔离晶体管的源读取为页缓冲器输出来直接触发页缓冲器输出的适当状态。

公开(公告)号：US07193921B2

公开(公告)日：2007-03-20

申请号：US11103047

申请日：2005-04-11

Applicant: Hyun-su Choi ,  Kyeong-rae Kim

Inventor： Hyun-su Choi ,  Kyeong-rae Kim

IPC: G11C5/14

CPC classification number: G11C7/22 ,  G11C7/20 ,  G11C2207/2227

Abstract: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

Abstract translation: 存储器件的唤醒电路使用级联链结构，其中位线被分成多个块，并且如果确定一个块的位线已经经历了基于位的唤醒操作 线路电压反馈到块中，在随后的块上执行唤醒操作。 因此，可以改变唤醒延迟，因此可以控制峰值电流，从而降低总体系统功率噪声。

公开(公告)号：US20070189086A1

公开(公告)日：2007-08-16

申请号：US11704089

申请日：2007-02-08

Applicant: Hyun-su Choi ,  Kyeong-rae Kim

Inventor： Hyun-su Choi ,  Kyeong-rae Kim

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/20 ,  G11C2207/2227

Abstract: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

公开(公告)号：US6160742A

公开(公告)日：2000-12-12

申请号：US353106

申请日：1999-07-14

Applicant: Min-Chul Chung ,  Kyeong-Rae Kim

Inventor： Min-Chul Chung ,  Kyeong-Rae Kim

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C16/02 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1039

Abstract: The semiconductor memory device includes a memory cell array, sense amplifying means for generating a sense output signal pair, and a data output buffer for providing the sense output signal pair. The data output buffer includes a level shifter for generating a first data output signal pair by shifting the level of the sense output signal pair responsive to the output buffer enable signal. A register inverts and latches the first data output signal pair, generating a second data output signal pair. A first transmission and latch means transmits and latches the second data output signal pair generating a third data output signal pair responsive to a first control signal. A second transmission and latch means transmits and latches the second data output signal pair generating a fourth data output signal pair responsive to a second control signal. A first inverter generates a fifth data output signal pair by inverting the third data output signal pair responsive to a first data output control signal. A second inverter generates the fifth data output signal pair by inverting the fourth data output signal pair responsive to a second data output control signal. A first latch generates a sixth data output signal pair by latching the fifth data output signal pair. A logical multiplication means manipulates the sixth data output signal pair responsive to an output enable signal.

Abstract translation: 半导体存储器件包括存储单元阵列，用于产生感测输出信号对的读出放大装置，以及用于提供感测输出信号对的数据输出缓冲器。 数据输出缓冲器包括电平移位器，用于通过根据输出缓冲器使能信号移位感测输出信号对的电平来产生第一数据输出信号对。 A寄存器反转并锁存第一数据输出信号对，产生第二数据输出信号对。 第一传输和锁存装置响应于第一控制信号发送和锁存产生第三数据输出信号对的第二数据输出信号对。 第二传输和锁存装置响应于第二控制信号发送和锁存产生第四数据输出信号对的第二数据输出信号对。 响应于第一数据输出控制信号，第一反相器通过使第三数据输出信号对反相来产生第五数据输出信号对。 第二反相器响应于第二数据输出控制信号，通过使第四数据输出信号对反相来产生第五数据输出信号对。 第一锁存器通过锁存第五数据输出信号对来产生第六数据输出信号对。 逻辑乘法装置响应于输出使能信号来操纵第六数据输出信号对。

公开(公告)号：US5487050A

公开(公告)日：1996-01-23

申请号：US229082

申请日：1994-04-18

Applicant: Kyeong-Rae Kim ,  Seung-Kweon Yang ,  Hee-Choul Park ,  Du-Eung Kim

Inventor： Kyeong-Rae Kim ,  Seung-Kweon Yang ,  Hee-Choul Park ,  Du-Eung Kim

IPC: G11C11/41 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C8/12

Abstract: A decoding circuit and method for a semiconductor memory device simplifies a decoding process by individually performing a large block decoding and small block decoding operations, and thereby reduces the total time delay taken in an address decoding process and layout area occupied by decoding circuits. The decoding circuit for a semiconductor memory device having a memory cell array including a plurality of large blocks, each large block including m small blocks (wherein m=2,3, . . . ) and having a plurality of memory cells being arranged in a matrix form, and a plurality of reading/writing circuits each corresponding to said large blocks, includes a first decoding circuit for receiving a first address to simultaneously select respective specific small block in each of the large blocks, corresponding to the first address, and a second decoding circuit for receiving a second address to enable a selected one of the reading/writing circuits corresponding to said second address.

Abstract translation: 用于半导体存储器件的解码电路和方法通过单独执行大块解码和小块解码操作简化了解码处理，从而减少了地址解码处理和解码电路所占用的布局区域的总时延。 一种具有包括多个大块的存储单元阵列的半导体存储器件的解码电路，每个大块包括m个小块（其中m = 2,3，...），并且具有多个存储单元 矩阵形式和与所述大块相对应的多个读/写电路包括：第一解码电路，用于接收第一地址以同时选择对应于第一地址的每个大块中的相应特定小块，以及 第二解码电路，用于接收第二地址以使得对应于所述第二地址的所述读/写电路中的所选择的一个。

公开(公告)号：US5471150A

公开(公告)日：1995-11-28

申请号：US171468

申请日：1993-12-22

Applicant: Chil-min Jung ,  Kyeong-rae Kim ,  Jeong-hee Lee

Inventor： Chil-min Jung ,  Kyeong-rae Kim ,  Jeong-hee Lee

IPC: G11C11/417 ,  G11C11/409 ,  G11C11/4093 ,  H03K5/13 ,  H03K17/16 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/20

CPC classification number: H03K19/01721 ,  H03K19/0013 ,  H03K19/00361

Abstract: An input buffer includes a low-speed input buffer for buffering an input signal at the time of low-speed operation, a high-speed input buffer being controlled by the low-speed input buffer, for adjusting the high-level and low-level logic of an input signal at the time of high-speed operation and an output driver for outputting high-level or low-level logic by inputting the output signal of the high-speed input buffer. Therefore, there is no direct current present, the operational speed is increased and noise can be reduced.

Abstract translation: 输入缓冲器包括用于在低速操作时缓冲输入信号的低速输入缓冲器，由低速输入缓冲器控制的高速输入缓冲器，用于调节高电平和低电平 高速操作时的输入信号的逻辑和通过输入高速输入缓冲器的输出信号来输出高电平或低电平逻辑的输出驱动器。 因此，不存在直流电，提高了运转速度，降低了噪音。