公开(公告)号：US6064609A

公开(公告)日：2000-05-16

申请号：US373447

申请日：1999-08-12

Applicant: Chul-Min Jung ,  Min-Chul Chung

Inventor： Chul-Min Jung ,  Min-Chul Chung

IPC: G11C29/04 ,  G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C29/781

Abstract: Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals. A second decoding means decodes the manipulated versions of the true and complement column address signals and generates third and fourth true decoded pulse signals and third and fourth complement decoded pulse signals. A sense amplification control signal generating means produces the sense amplification control signal responsive to the first, second, third, and fourth true decoded pulse signals and the first, second, third, and fourth complement decoded pulse signals. A row select signal generating means produces the row select signal responsive to first, second, third, and fourth true decoded pulse signals. The above-described redundancy controller improves the redundancy speed.

Abstract translation: 公开了一种包括冗余控制器的半导体存储器件。 冗余控制器使用传递门逻辑，动态反相器电路和真/补码解码器方案构成。 冗余控制器包括分别对应于第一和第二冗余列的第一和第二冗余使能电路。 第一和第二保险丝盒分别耦合到第一和第二冗余使能电路。 第一和第二保险丝盒各自包括对应于列地址信号的熔丝盒电路和熔丝元件。 每个保险丝盒电路接收相应的一对真和补列列地址信号，并响应于熔丝元件操纵真和补列列地址信号。 第一解码装置对真和补列列地址信号的操纵版本进行​​解码，并产生第一和第二真解码脉冲信号以及第一和第二补码解码脉冲信号。 第二解码装置解码真和补列列地址信号的操纵版本，并产生第三和第四真实解码脉冲信号以及第三和第四补码解码脉冲信号。 感测放大控制信号产生装置响应于第一，第二，第三和第四真实解码脉冲信号以及第一，第二，第三和第四补码解码脉冲信号产生感测放大控制信号。 行选择信号发生装置响应于第一，第二，第三和第四真实解码脉冲信号产生行选择信号。 上述冗余控制器提高冗余速度。

公开(公告)号：US06275069B1

公开(公告)日：2001-08-14

申请号：US09222497

申请日：1998-12-29

Applicant: Min-Chul Chung ,  Chul-Min Jung

Inventor： Min-Chul Chung ,  Chul-Min Jung

IPC: H03K19096

CPC classification number: H03K19/0963 ,  H03K19/01721

Abstract: A self-resetting circuit includes a logic circuit operative to transition an output signal from a first logic state to a second logic state responsive to a first logic state transition of an input signal, along with a bistable reset circuit coupled to the logic circuit and operative to be triggered by the transition of the output signal from the first logic state to the second logic state to reset the output signal to the first logic state within a first predetermined interval following the transition of the output signal from the first logic state to the second logic state, and to be armed by a second logic state transition of the input signal next succeeding the first logic state transition, wherein the reset circuit is armed within a second predetermined interval following the second transition that is less than the first predetermined interval. Related operating methods are also discussed.

Abstract translation: 自复位电路包括逻辑电路，其可操作以响应于输入信号的第一逻辑状态转换而将输出信号从第一逻辑状态转换到第二逻辑状态，以及耦合到逻辑电路的双稳态复位电路和操作 由输出信号从第一逻辑状态到第二逻辑状态的转变触发，以在输出信号从第一逻辑状态转换到第二逻辑状态之后的第一预定间隔内将输出信号复位到第一逻辑状态 逻辑状态，并且由第二逻辑状态转换之后的输入信号的第二逻辑状态转换来布防，其中，所述复位电路布防在所述第二转换之后的第二预定间隔内小于所述第一预定间隔。 还讨论了相关的操作方法。

公开(公告)号：US5384736A

公开(公告)日：1995-01-24

申请号：US143895

申请日：1993-11-01

Applicant: Chul-Min Jung ,  Young-Ho Suh

Inventor： Chul-Min Jung ,  Young-Ho Suh

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409 ,  H03K17/30 ,  H03K17/687 ,  H03K19/0175 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1048 ,  G11C7/1051

Abstract: A data output circuit of a semiconductor memory device matches an equalizing level of voltages at data lines in a pair with a logic threshold voltage of data output buffers. The data output circuit having an equalizing transistor connected between first and second nodes connected to the outputs of a sense amplifier, includes a threshold voltage control circuit disposed between the sense amplifier and the data output buffers for allowing a threshold voltage of the data output buffers to match with the equalizing level of the voltages at the first and second nodes. The threshold voltage control circuit has the same structure and characteristics as that of the output buffers, so as to ensure that the logic threshold voltage of the data output buffers matches with the equalizing level of the voltages at the first and second nodes.

Abstract translation: 半导体存储器件的数据输出电路将数据线上的电压与数据输出缓冲器的逻辑阈值电压相匹配。 连接在连接到读出放大器的输出的第一和第二节点之间的具有均衡晶体管的数据输出电路包括设置在感测放大器和数据输出缓冲器之间的阈值电压控制电路，用于允许数据输出缓冲器的阈值电压 与第一和第二节点处的电压的均衡电平相匹配。 阈值电压控制电路具有与输出缓冲器相同的结构和特性，以确保数据输出缓冲器的逻辑阈值电压与第一和第二节点处的电压的均衡电平相匹配。

公开(公告)号：US5777931A

公开(公告)日：1998-07-07

申请号：US703204

申请日：1996-08-26

Applicant: Ig-Soo Kwon ,  Chul-Min Jung

Inventor： Ig-Soo Kwon ,  Chul-Min Jung

IPC: G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/842

Abstract: Redundancy decoding systems and methods for integrated circuit memory devices synchronize a redundancy decoding signal to allow the redundancy decoding signal to be output during an enabling period and to prevent output of the redundancy decoding signal otherwise. In particular, a redundancy decoder is synchronized to an output buffer so that the redundancy decoder generates a redundancy decoding signal during a time period which is independent of the identity of the programmed address. Accordingly, high speed selection of a redundancy word line is provided in synchronism with the conventional word line selection, so that address skew and improper operation of the redundancy system relative to the normal word line selection system is prevented.

Abstract translation: 用于集成电路存储器件的冗余解码系统和方法使冗余解码信号同步，以允许在使能期间输出冗余解码信号，并且防止冗余解码信号的输出。 特别地，冗余解码器被同步到输出缓冲器，使得冗余解码器在与编程地址的身份无关的时间段期间产生冗余解码信号。 因此，与常规字线选择同步地提供冗余字线的高速选择，从而防止冗余系统相对于正常字线选择系统的地址偏移和不正确的操作。

公开(公告)号：US6023177A

公开(公告)日：2000-02-08

申请号：US988312

申请日：1997-12-11

Applicant: Eun-Cheol Kim ,  Chul-Min Jung

Inventor： Eun-Cheol Kim ,  Chul-Min Jung

IPC: G11C11/407 ,  G06F12/02 ,  G11C7/10 ,  G11C11/41 ,  G11C11/413 ,  H03L7/00

CPC classification number: G11C7/1072 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1078

Abstract: A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

Abstract translation: 一种用于提供突发模式控制信号的半导体存储器件。 半导体存储器件包括：第一逻辑电路，用于响应于外部输入的写入和读取控制信号和外部输入的芯片使能信号的第一逻辑电平产生驱动信号;多个转换寄存器，用于分别改变驱动信号 与时钟信号的第一边沿同步以产生改变的驱动信号;以及第二逻辑电路，用于响应于读等待时间控制信号而产生由所改变的驱动信号的逻辑组合产生的突发模式控制信号。

公开(公告)号：US6011421A

公开(公告)日：2000-01-04

申请号：US994911

申请日：1997-12-19

Applicant: Chul-Min Jung

Inventor： Chul-Min Jung

IPC: H03K19/0185 ,  G11C7/00 ,  H03K3/356 ,  H03K17/10 ,  H03L5/00

CPC classification number: H03K3/356113 ,  H03K17/102

Abstract: A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Abstract translation: 可升级的电平转换器，可以高速执行并优化功耗。 可扩展电平移位器接收输入信号并将具有可伸缩电压电平的输入信号转换为具有预定电压电平的输出信号。 可扩展电平移位器包括连接到内部电源的自复位电路，用于响应于对应于输入信号的电压转换的输出信号电压变化来中断内部电流通路。

公开(公告)号：US5699304A

公开(公告)日：1997-12-16

申请号：US653056

申请日：1996-05-24

Applicant: Chul-Min Jung ,  Seung-Kweon Yang

Inventor： Chul-Min Jung ,  Seung-Kweon Yang

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C11/407 ,  H03K3/356 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356026 ,  H03K3/356121

Abstract: A level converter for use in a semiconductor memory device includes a level converting unit, a latch circuit and a blocking circuit. The level converting unit receives sensed first and second sensing voltages and a control clock and which provides level-converted first and second output voltages in correspondence with the first and second sensing voltage at first and second output nodes in response to the control clock. The latch circuit boosts a difference between the first and second output voltages provided at the first and second output nodes to be substantially equal to the level of a supply voltage in response to the application of the supply voltage. The blocking circuit controls the application of the supply voltage to the level converting unit and the latch circuit according to the control clock, in order to reduce current consumption due to the application of the supply voltage and to achieve a high operating speed.

Abstract translation: 用于半导体存储器件的电平转换器包括电平转换单元，锁存电路和阻塞电路。 电平转换单元接收感测的第一和第二感测电压和控制时钟，并且响应于控制时钟，在第一和第二输出节点处对应于第一和第二感测电压提供电平转换的第一和第二输出电压。 锁存电路将提供在第一和第二输出节点处的第一和第二输出电压之间的差异升高为响应于施加电源电压而基本上等于电源电压的电平。 阻塞电路根据控制时钟控制向电平转换单元和锁存电路施加电源电压，以便降低由于施加电源电压引起的电流消耗并实现高的运行速度。

公开(公告)号：US5592121A

公开(公告)日：1997-01-07

申请号：US358929

申请日：1994-12-19

Applicant: Chul-Min Jung ,  Hee-Choul Park

Inventor： Chul-Min Jung ,  Hee-Choul Park

IPC: G11C11/407 ,  G05F1/46 ,  G05F1/56 ,  G11C5/14 ,  H01L21/822 ,  H01L27/04

CPC classification number: G05F1/465

Abstract: Semiconductor integrated circuits, and more particularly an internal power-supply voltage supplier, can be adapted to high density memory devices, for providing a converted external power-supply voltage as an internal power-supply voltage having a desired potential. An internal power-supply voltage supplier receives a reference signal and an internal power-supply voltage signal and provides a semiconductor integrated circuit with an internal power-supply voltage having a desired voltage level by way of a driver, and comprises an offset generator connected to the driver, including two transistors having different width-length characteristics, for receiving the reference signal and the internal power-supply voltage signal and producing an offset corresponding to the received signals, the internal power-supply voltage is provided at a desired voltage level by the driver when the offset generator performs an offset operation.

Abstract translation: 半导体集成电路，更具体地，内部电源电压供应器可以适用于高密度存储器件，用于提供转换的外部电源电压作为具有期望电位的内部电源电压。 内部电源电压供应器接收参考信号和内部电源电压信号，并通过驱动器向半导体集成电路提供具有期望电压电平的内部电源电压，并且包括偏移发生器，连接到 驱动器包括具有不同宽度长度特性的两个晶体管，用于接收参考信号和内部电源电压信号并产生对应于接收信号的偏移，内部电源电压以期望的电压电平提供在期望的电压电平 当偏移发生器执行偏移操作时，驱动器。