公开(公告)号：US08039274B2

公开(公告)日：2011-10-18

申请号：US12385945

申请日：2009-04-24

申请人： Sang-Jib Han

发明人： Sang-Jib Han

IPC分类号： H01L21/66

CPC分类号： G01R31/318513 ,  G01R31/31717

摘要： A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.

摘要翻译： 半导体芯片可以包括用于接收外部电源电压的至少一个电源焊盘，至少一个输入/输出焊盘，内部功能块，其可以被配置为基于电源电压来操作以至少接收和发送一个 信号通过输入/输出焊盘，以及模式设置电路，其可以在单独芯片测试模式中通过模式设置信号来启用或禁用电源电压。

公开(公告)号：US20070045827A1

公开(公告)日：2007-03-01

申请号：US11508176

申请日：2006-08-23

申请人： Sang-jib Han ,  Jai-kyeong Shinn

发明人： Sang-jib Han ,  Jai-kyeong Shinn

IPC分类号： H01L23/34

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

摘要翻译： 一种半导体多芯片封装，包括：具有n个地址焊盘的第一半导体存储器芯片，第一控制焊盘和第一地址控制器; 以及第二半导体存储器芯片，其存储密度比第一半导体存储器芯片大，比第一半导体存储器芯片大至少1.5倍，并且设置在第一半导体存储器芯片上，并且具有（n + 1）个地址焊盘，第二控制 垫和第二地址控制器。 第一半导体存储器芯片的n个地址焊盘和第二半导体存储器芯片的n个地址焊盘分别连接到相应的n个地址引脚。 第一和第二控制焊盘连接到控制引脚。 根据施加到控制引脚的信号，第一和第二地址控制器可以互相排斥的方式操作，例如激活的方式。

公开(公告)号：US07154790B2

公开(公告)日：2006-12-26

申请号：US11001343

申请日：2004-12-01

申请人： Sang-Jib Han ,  Chang-Hwan Lee

发明人： Sang-Jib Han ,  Chang-Hwan Lee

IPC分类号： G11C5/14

CPC分类号： G11C29/12 ,  G11C5/04 ,  G11C16/04 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/1202 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips includes a high voltage generator configured to receive an input voltage through the common input/output pad and generate a test voltage responsive to a test mode signal during a test mode of operation. The test voltage is higher than the input voltage. Related methods of operating integrated circuit devices and semiconductor devices are also provided.

公开(公告)号：US06288926B1

公开(公告)日：2001-09-11

申请号：US09535871

申请日：2000-03-27

申请人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

发明人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C11/412

摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

摘要翻译： 公开了一种半导体存储器件。 该装置由多条字线组成; 垂直于字线布置的多个位线。 此外，多个电源电压线沿与位线相同的方向延伸。 此外，多个第一接地电压线被布置在与位线相同的方向上。 此外，多个第二接地电压线布置在与字线相同的方向上。 多个存储单元分别连接在一条字线和一条位线之间。 这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止 装置。

公开(公告)号：US06271705B1

公开(公告)日：2001-08-07

申请号：US09448534

申请日：1999-11-22

申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： H03K500

CPC分类号： H01L27/0266

摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

公开(公告)号：US07486532B2

公开(公告)日：2009-02-03

申请号：US11508176

申请日：2006-08-23

申请人： Sang-jib Han ,  Jai-kyeong Shinn

发明人： Sang-jib Han ,  Jai-kyeong Shinn

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

摘要翻译： 一种半导体多芯片封装，包括：具有n个地址焊盘的第一半导体存储器芯片，第一控制焊盘和第一地址控制器; 以及第二半导体存储器芯片，其存储密度比第一半导体存储器芯片大，比第一半导体存储器芯片大至少1.5倍，并且设置在第一半导体存储器芯片上，并且具有（n + 1）个地址焊盘，第二控制 垫和第二地址控制器。 第一半导体存储器芯片的n个地址焊盘和第二半导体存储器芯片的n个地址焊盘分别连接到相应的n个地址引脚。 第一和第二控制焊盘连接到控制引脚。 根据施加到控制引脚的信号，第一和第二地址控制器可以互相排斥的方式操作，例如激活的方式。

公开(公告)号：US06816429B2

公开(公告)日：2004-11-09

申请号：US10268380

申请日：2002-10-09

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置变换选择的存储器件的地址，并响应于时钟信号产生地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选择的存储器件。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储器件顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US06510094B2

公开(公告)日：2003-01-21

申请号：US09940909

申请日：2001-08-28

申请人： Min-Chul Chung ,  Chang-Rae Kim ,  Sang-Jib Han ,  Jong-Yul Park

发明人： Min-Chul Chung ,  Chang-Rae Kim ,  Sang-Jib Han ,  Jong-Yul Park

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C11/406

摘要： Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.

摘要翻译： 公开了一种半导体存储器件，包括多个子字线驱动器，其布置在位线方向上的所有存储单元阵列块上，并分别由两个存储单元阵列块共享;多个块读出放大器，布置在所有存储单元 并且分别由两个存储单元阵列块共享的多个电路块，分别布置在容纳子字线驱动器和块读出放大器的区域的连接区域; 所述连接区域包括适于驱动块读出放大器的一个或多个LA驱动器，适于产生用于控制子字线驱动器的驱动控制信号的一个或多个PXiD电路以及适于选择性地使LA驱动器响应的一个或多个BSYD电路 传输块控制信号; 以及多个块控制单元，适于通过组合列和行块地址解码信号并且同时使用块控制信号激活两个或更多个BSYD电路来生成上部和下部块控制信号。

公开(公告)号：US06490223B1

公开(公告)日：2002-12-03

申请号：US09614783

申请日：2000-07-12

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C800

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置对所选存储单元的地址进行变换，并根据时钟信号生成地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选定的存储单元。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储单元顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US20090212812A1

公开(公告)日：2009-08-27

申请号：US12385945

申请日：2009-04-24

申请人： Sang-Jib Han

发明人： Sang-Jib Han

IPC分类号： G01R31/26

CPC分类号： G01R31/318513 ,  G01R31/31717

摘要： A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.