公开(公告)号：US07696570B2

公开(公告)日：2010-04-13

申请号：US12350708

申请日：2009-01-08

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

公开(公告)号：US20090114999A1

公开(公告)日：2009-05-07

申请号：US12350708

申请日：2009-01-08

申请人： Hyeoung-Won SEO ,  Du-Heon SONG ,  Sang-Hyun LEE

发明人： Hyeoung-Won SEO ,  Du-Heon SONG ,  Sang-Hyun LEE

IPC分类号： H01L29/66 ,  H01L23/48 ,  H01L27/108 ,  H01L49/00

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

公开(公告)号：US07524733B2

公开(公告)日：2009-04-28

申请号：US11735919

申请日：2007-04-16

申请人： Hyeoung-Won Seo ,  Nak-Jin Son ,  Du-Heon Song ,  Jun Seo

发明人： Hyeoung-Won Seo ,  Nak-Jin Son ,  Du-Heon Song ,  Jun Seo

IPC分类号： H01L21/76

CPC分类号： H01L29/66636 ,  H01L29/78 ,  Y10S438/942

摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

摘要翻译： 根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层 离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案 ，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。 因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

公开(公告)号：US20060118885A1

公开(公告)日：2006-06-08

申请号：US11284237

申请日：2005-11-21

申请人： Du-Heon Song

发明人： Du-Heon Song

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/0629 ,  H01L27/0688 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/20 ,  H01L28/91

摘要： In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad is disposed on the lower interlayer insulating layer in the cell region. A capacitor is provided to have a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric is interposed between the storage node electrode and the plate electrode. A lower resistor is disposed on the lower interlayer insulating layer in the peripheral region. 10 An upper resistor is disposed on the lower resistor to expose both ends of the lower resistor. An inter-resistor insulating layer is interposed at least between the lower resistor and the upper resistor. An upper interlayer insulating layer is disposed on the lower interlayer insulating layer to cover the capacitor, the lower resistor, and the upper resistor. A resistor interconnection line is disposed on the upper interlayer insulating layer, to contact a resistor contact plug penetrating the upper interlayer insulating layer and is electrically connected to a first end of the lower resistor and a first end of the upper resistor.

摘要翻译： 在具有电阻器的半导体器件及其制造方法中，该器件包括具有单元区域和周边区域的半导体衬底。 下半层绝缘层设置在半导体衬底上。 缓冲垫设置在电池区域中的下层间绝缘层上。 设置电容器以具有设置在缓冲垫上的存储节点电极，覆盖存储节点电极的平板电极和电容器电介质介于存储节点电极和平板电极之间。 下部电阻器设置在周边区域的下部层间绝缘层上。 10上电阻设在下电阻上，露出下电阻的两端。 至少在下电阻器和上电阻器之间插入有电阻器绝缘层。 上层间绝缘层设置在下层绝缘层上以覆盖电容器，下电阻器和上电阻器。 电阻器互连线设置在上层间绝缘层上，以接触穿过上层间绝缘层的电阻器接触插塞，并且电连接到下电阻器的第一端和上电阻器的第一端。

公开(公告)号：US20050208715A1

公开(公告)日：2005-09-22

申请号：US11083660

申请日：2005-03-16

申请人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Yoon

发明人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Yoon

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L29/66818

摘要： Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.

摘要翻译： 公开了制造鳍式场效应晶体管（FinFET）的方法。 本发明的实施例提供了通过优化用于形成翅片的方法来制造FinFET的方法，使得防止短通道效应并实现高集成度。 因此，可以容易地形成使用当前的光刻蚀刻技术难以形成的翅片。

公开(公告)号：US20050179030A1

公开(公告)日：2005-08-18

申请号：US10938436

申请日：2004-09-09

申请人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Yoon

发明人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Yoon

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.

摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。 沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。 栅极线形成为覆盖并延伸穿过通道散热片。 源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。 描述和要求保护其他实施例。