公开(公告)号：US20130033938A1

公开(公告)日：2013-02-07

申请号：US13483308

申请日：2012-05-30

Applicant: Sang-Soo Park ,  Jae-Yong Jeong

Inventor： Sang-Soo Park ,  Jae-Yong Jeong

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3454

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

Abstract translation: 通过执行多个程序循环来编程非易失性存储器件，每个程序循环包括对所选择的字线施加编程电压以改变所选择的存储单元的阈值电压，以及将验证电压施加到所选择的字线以验证 选择的存储单元。 在每个程序循环中，非易失性存储器件确定程序状态，并使程序电压递增根据程序条件确定的量。

公开(公告)号：US08154920B2

公开(公告)日：2012-04-10

申请号：US12712769

申请日：2010-02-25

Applicant: In-Mo Kim ,  Jae-Yong Jeong

Inventor： In-Mo Kim ,  Jae-Yong Jeong

IPC: G11C16/04

CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/32

Abstract: A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

Abstract translation: 一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序 在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。 在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间 级存储单元，并根据开始地址按顺序读取数据。

公开(公告)号：US07623376B2

公开(公告)日：2009-11-24

申请号：US12035346

申请日：2008-02-21

Applicant: Jung-Woo Lee ,  Jae-Yong Jeong

Inventor： Jung-Woo Lee ,  Jae-Yong Jeong

IPC: G11C11/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract translation: 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07580281B2

公开(公告)日：2009-08-25

申请号：US11969969

申请日：2008-01-07

Applicant: Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C11/34

CPC classification number: G11C16/22

Abstract: A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering the temporary protected/accessible data.

Abstract translation: 公开了一种闪存设备和写保护数据的相关方法。 闪存设备包括保护控制器，其具有存储临时保护/可访问数据的锁存电路，存储持久保护/可访问数据的单元阵列，改变永久保护/可访问数据的写控制器以及改变临时保护/可访问的锁存器控制器 数据。

公开(公告)号：US07542354B2

公开(公告)日：2009-06-02

申请号：US11634058

申请日：2006-12-05

Applicant: Jin-Young Chun ,  Jae-Yong Jeong

Inventor： Jin-Young Chun ,  Jae-Yong Jeong

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C16/26 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract translation: 非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。 该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。 重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作 州。

公开(公告)号：US07525838B2

公开(公告)日：2009-04-28

申请号：US11642925

申请日：2006-12-21

Applicant: Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming.

Abstract translation: 提供一种用于对闪速存储器件进行编程的方法，其中闪速存储器件包括多个存储器单元，并且其中每个存储器单元的阈值电压可以以多个对应的数据状态中的任何一个来编程。 该方法包括以第一数据状态编程所选择的存储器单元，验证编程结果，以对应于低于第一数据状态的对应阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选择的存储器单元 ，并验证连续编程的结果。

公开(公告)号：US07447067B2

公开(公告)日：2008-11-04

申请号：US11453991

申请日：2006-06-16

Applicant: Jae-Phil Kong ,  Jae-Yong Jeong

Inventor： Jae-Phil Kong ,  Jae-Yong Jeong

IPC: G11C11/34

CPC classification number: G11C16/102 ,  G11C11/5628 ,  G11C2211/5621

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract translation: 一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态， 确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线 记忆单元

公开(公告)号：US20080170436A1

公开(公告)日：2008-07-17

申请号：US11969969

申请日：2008-01-07

Applicant: Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

Inventor： Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

IPC: G11C16/04

CPC classification number: G11C16/22

Abstract: A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering the temporary protected/accessible data.

Abstract translation: 公开了一种闪存设备和写保护数据的相关方法。 闪存设备包括保护控制器，其具有存储临时保护/可访问数据的锁存电路，存储持久保护/可访问数据的单元阵列，改变永久保护/可访问数据的写控制器以及改变临时保护/可访问的锁存器控制器 数据。

公开(公告)号：US20080158993A1

公开(公告)日：2008-07-03

申请号：US11763606

申请日：2007-06-15

Applicant: Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C16/28

CPC classification number: G11C16/3454

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.

Abstract translation: 驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元 并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。 非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器 验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和 所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。