公开(公告)号：US09478285B2

公开(公告)日：2016-10-25

申请号：US14800060

申请日：2015-07-15

Applicant: Hyun-Kook Park ,  Chi-Weon Yoon ,  Dae-Seok Byeon

Inventor： Hyun-Kook Park ,  Chi-Weon Yoon ,  Dae-Seok Byeon

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5642 ,  G11C13/0002 ,  G11C2013/0054 ,  G11C2213/71

Abstract: A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.

Abstract translation: 一种操作具有多电平单元阵列的交叉点存储器件的方法包括通过多个感测操作执行关于多电平单元的第一读取操作，以确定第一状态并执行关于第二读取操作的第二读取操作 所述多电平单元通过多个感测操作来确定第二状态。 在第一读取操作中使用的第一电压的电平与在第一读取操作中的第二感测操作中使用的第二电压的电平之间的差异不同于在第一感测中使用的第三电压的电平之间的差 操作和在第二读取操作中的第二感测操作中使用的第四电压的电平。

公开(公告)号：US20160125942A1

公开(公告)日：2016-05-05

申请号：US14800727

申请日：2015-07-16

Applicant: CHI-WEON YOON ,  HYUN-KOOK PARK ,  DAE-SEOK BYEON

Inventor： CHI-WEON YOON ,  HYUN-KOOK PARK ,  DAE-SEOK BYEON

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

公开(公告)号：US20150370705A1

公开(公告)日：2015-12-24

申请号：US14837857

申请日：2015-08-27

Applicant: Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

Inventor： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

IPC: G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0646 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F2212/2022 ,  G11C5/025 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract translation: 至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度 字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或 自然数大于2。

公开(公告)号：US09030869B2

公开(公告)日：2015-05-12

申请号：US13584847

申请日：2012-08-14

Applicant: Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

Inventor： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

IPC: G11C11/34 ,  G11C7/22 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483

Abstract: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Abstract translation: 三维（3D）半导体存储器件包括存储单元串，每个存储单元串包括至少一个选择晶体管和至少一个存储单元，共享第一阱区的第一级晶体管组，并且包括连接到选择的第一选择线传输晶体管 晶体管和连接到存储单元的第一世界线传输晶体管，第二传输晶体管组共享第二阱区并且包括连接到选择晶体管的第二选择线传输晶体管，以及控制器，其控制第一传输晶体管组和 二级晶体管组。 控制器在读取操作期间将选择的电压施加到第一和第二阱区。

公开(公告)号：US08570808B2

公开(公告)日：2013-10-29

申请号：US13186987

申请日：2011-07-20

Applicant: Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

Inventor： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

Abstract: A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

Abstract translation: 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

公开(公告)号：US08359424B2

公开(公告)日：2013-01-22

申请号：US12591198

申请日：2009-11-12

Applicant: Jae-phil Kong ,  Chi-weon Yoon

Inventor： Jae-phil Kong ,  Chi-weon Yoon

IPC: G06F12/00

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C2211/5641

Abstract: Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.

Abstract translation: 提供了闪速存储装置和闪存装置的读取方法。 多级单元闪存器件包括：存储单元阵列，包括存储主数据的主存储单元，存储指示单元的指示单元表示指示主存储单元的主数据的第一模式和第二模式之一的数据， 指示单元对应的; 以及输出单元，响应于与指示数据相对应的控制信号，从存储器单元阵列读取的主数据中的一个和强制数据将主数据的某些位值强制为模式特定数据的位值作为读取数据。

公开(公告)号：US08347183B2

公开(公告)日：2013-01-01

申请号：US12486875

申请日：2009-06-18

Applicant: Chi-weon Yoon ,  Chae-hoon Kim

Inventor： Chi-weon Yoon ,  Chae-hoon Kim

IPC: H03M13/00

CPC classification number: G06F11/1068 ,  G11C16/16 ,  G11C16/3454

Abstract: A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

Abstract translation: 一种使用纠错码（ECC）算法的闪存器件及其操作方法。 该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于 闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。 一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。

公开(公告)号：US20120033501A1

公开(公告)日：2012-02-09

申请号：US13186987

申请日：2011-07-20

Applicant: Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

Inventor： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

Abstract: Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

Abstract translation: 公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路 信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。 所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

公开(公告)号：US07800944B2

公开(公告)日：2010-09-21

申请号：US12129820

申请日：2008-05-30

Applicant: Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

Abstract translation: 公开了一种非易失性存储器件的非易失性存储器件和编程方法。 非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作 比第一编程操作的第一验证电压。

公开(公告)号：US20090327839A1

公开(公告)日：2009-12-31

申请号：US12486875

申请日：2009-06-18

Applicant: Chi-weon Yoon ,  Chae-hoon Kim

Inventor： Chi-weon Yoon ,  Chae-hoon Kim

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G11C16/16 ,  G11C16/3454

Abstract: A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

Abstract translation: 一种使用纠错码（ECC）算法的闪存器件及其操作方法。 该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于 闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。 一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。