Abstract:
A flow control system and methodology controls and avoids congestion in an Asynchronous Transfer Mode (ATM) network. The congestion state of a network switch is determined based on incoming Available Bit Rate (ABR) traffic, Constant Bit Rate (CBR) traffic, and Variable Bit Rate (VBR) traffic. High-frequency fluctuations due to VBR traffic are filtered out of the CBR/VBR traffic to determine the underlying trend of network traffic. A filtering mechanism is based on wavelet transforms. The switch congestion state is determined based on the current ABR traffic, the filtered CBR/VBR traffic, and the current status of buffers in the switch. The congestion state can then be used to adjust the ABR rate according to a feedback scheme such as Explicit Forward Congestion Indication (EFCI).
Abstract:
In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.
Abstract:
This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock.
Abstract:
A timing system for time synchronization between a time server and a time client over a packet network. The timing system includes a time server for generating current timestamp information and a time client having a phase-locked loop driven client clock counter. The time client periodically exchanges time transfer protocol messages with the time server over the packet network, and calculates an estimated client time based on the timestamp information. The phase-locked loop in the time client receives periodic signals representing the estimated server time as its input and calculates a signal which represents the error difference between the estimated server time and the time indicated by the time client clock counter. The error difference eventually converges to zero or a given error range indicating the time presented by the client clock counter, which is driven by the phase-locked loop having locked onto the time of the time server.
Abstract:
Algorithms and data structure are described for constructing and maintaining a clock distribution tree (“CDT”) for timing loop avoidance. The CDT algorithms and data structure allows a node to make an automated and unattended path switch to the most desirable clock source in the network. In response to a network topology change, a clock root node distributes new clock paths to all nodes in the network. In particular, the root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.
Abstract:
Techniques for time transfer via signal encoding are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for time transfer via signal encoding comprising generating a time service ordered-set for inclusion in a physical coding sublayer frame of a physical layer device, generating time service data for inclusion in the physical coding sublayer frame of the physical layer device, and transmitting the physical coding sublayer frame.
Abstract:
A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.
Abstract:
The invention includes a technique for clock recovery in a network having master and slave clocks in respective Time Division Multiplexing (“TDM”) network segments which are interconnected by a non-TDM segment. Master clock timestamps are sent to the slave. The slave measures a master clock timestamp inter-arrival interval, and sends slave clock timestamps to the master. The master measures a slave clock timestamp inter-arrival interval, and sends that slave clock timestamp inter-arrival interval to the slave. The slave then calculates an error signal based at least in-part on the difference between the master clock timestamp inter-arrival interval and the slave clock timestamp inter-arrival interval, and employs the difference to recover the first service clock in the second TDM segment.
Abstract:
Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).
Abstract:
A novel beacon-based position location technique for efficient location discovery of untethered clients in packet networks is disclosed. The position location technique utilizes the time-difference-of-arrival (“TDOA”) of a first signal transmitted by a beacon of known location and a second signal transmitted by an untethered client. The TDOA of these two signals is measured locally by at least three non-collinear signal receivers. For each of the receivers, the TDOA is used to calculate a perceived distance to the client. A circle is then calculated for each receiver, centered on the receiver and having a radius equal to the perceived distance. At least two lines defined by points of intersection of the calculated circles are then calculated. The point of intersection of the lines represents the location of the client. To facilitate operation, the signal receivers may be arranged on vertices which define a convex polygon as viewed from above. The location system requires no time (time-of-day) synchronization of the signal receivers, and only the coarse frequency synchronization, on the order of, tens of parts-per-million (ppm). The technique even works for the case where the signal receivers are run asynchronously, provided the frequency accuracies of the signal receivers are on the order of about 50 ppm or better. The technique introduces no communication overhead for the beacon, client and signal receivers. Further, the computation overhead at the signal receivers is relatively low because the location detection algorithm involves only simple algebraic operations over scalar values.