中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

68 records (took 0.025 seconds)

    Automated sensitivity definition and calibration for design for manufacturing tools
    41.
    发明授权
    Automated sensitivity definition and calibration for design for manufacturing tools 有权
    自动灵敏度定义和校准用于制造工具的设计

    公开(公告)号：US08141027B2

    公开(公告)日：2012-03-20

    申请号：US12652409

    申请日：2010-01-05

    Applicant: James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    Inventor： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

    Abstract translation: 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

    Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
    42.
    发明授权
    Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool 有权
    使用关键区域分析工具计算VLSI设计对随机和系统缺陷的敏感度的方法

    公开(公告)号：US08132129B2

    公开(公告)日：2012-03-06

    申请号：US12348070

    申请日：2009-01-02

    Applicant: Jeanne P. Bickford ,  Jason D. Hibbeler ,  Juergen Koehl

    Inventor： Jeanne P. Bickford ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

    Abstract translation: 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预先扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时预结构。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。

    IMAGE SENSOR PIXEL STRUCTURE EMPLOYING A SHARED FLOATING DIFFUSION
    44.
    发明申请
    IMAGE SENSOR PIXEL STRUCTURE EMPLOYING A SHARED FLOATING DIFFUSION 有权
    图像传感器像素结构采用共享浮动扩展

    公开(公告)号：US20110025892A1

    公开(公告)日：2011-02-03

    申请号：US12534427

    申请日：2009-08-03

    Applicant: Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin N. Ogg ,  Richard J. Rassel

    Inventor： Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin N. Ogg ,  Richard J. Rassel

    IPC: H04N5/335 ,  H01L31/112 ,  G06F17/50

    CPC classification number: H01L27/14609 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/37457

    Abstract: A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.

    Abstract translation: 图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。 四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。 四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。 公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

    Integrated circuit selective scaling
    45.
    发明授权
    Integrated circuit selective scaling 有权
    集成电路选择性缩放

    公开(公告)号：US07882463B2

    公开(公告)日：2011-02-01

    申请号：US12035572

    申请日：2008-02-22

    Applicant: Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    Inventor： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

    Abstract translation: 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。

    Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique
    46.
    发明授权
    Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique 有权
    基于使用开放确定性测序技术选择的样本窗口来分析集成电路的方法和系统

    公开(公告)号：US07752580B2

    公开(公告)日：2010-07-06

    申请号：US11828728

    申请日：2007-07-26

    Applicant: Sarah C. Braasch ,  Jason D. Hibbeler ,  Rouwaida N. Kanj ,  Daniel N. Maynard ,  Sani R. Nassif ,  Evanthia Papadopoulou

    Inventor： Sarah C. Braasch ,  Jason D. Hibbeler ,  Rouwaida N. Kanj ,  Daniel N. Maynard ,  Sani R. Nassif ,  Evanthia Papadopoulou

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

    Abstract translation: 这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。 在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。 然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。 这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

    METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL
    48.
    发明申请
    METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL 有权
    使用关键领域分析工具计算VLSI设计对两个随机和系统缺陷的敏感度的方法

    公开(公告)号：US20090113360A1

    公开(公告)日：2009-04-30

    申请号：US12348070

    申请日：2009-01-02

    Applicant: JEANNE P. BICKFORD ,  Jason D. Hibbeler ,  Juergen Koehl

    Inventor： JEANNE P. BICKFORD ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

    Abstract translation: 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时，预结构化。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。

    POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS
    50.
    发明申请
    POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS 审中-公开
    用于VLSI LAYOUTS的多边形设计规则校正方法

    公开(公告)号：US20090037850A1

    公开(公告)日：2009-02-05

    申请号：US11831990

    申请日：2007-08-01

    Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

    Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last “next LP problem” is solved using constraints and objectives representing sums or differences of no more than two optimization variables.

    Abstract translation: 一种多边形区域设计规则校正方法，用于电子设计自动化工具，用于使用一维（1-D）优化来管理集成电路（IC）设计布局，并分析IC设计布局数据以识别违反多边形，划分 在优化方向上将多边形侵入矩形，为每个违规多边形制定面积约束以制定全局线性规划（LP）问题，其包括每个违反多边形的每个约束，并解决全局LP问题以获得实值解。 为每个区域约束创建下一个LP问题，并解决。 重复创建下一个LP并解决下一个LP问题和解决问题，直到最后的“下一个LP问题”使用表示不超过两个优化变量的和或差的约束和目标来解决。

Patent Agency Ranking