公开(公告)号：US07339851B2

公开(公告)日：2008-03-04

申请号：US11618984

申请日：2007-01-02

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C8/14

Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.

Abstract translation: 这里公开了通过使用具有两个晶体管的子字线驱动器防止子字线浮动的字线驱动电路。 多个子字线驱动器连接到一个主字线。 多个子字线中的每一个包括PMOS晶体管和串联连接在子字线驱动电压FX与接地电压之间的NMOS晶体管。 浮动防止单元使用具有阈值电压电平的驱动信号来选择主字线为阈值电平的电平，从而防止子字线驱动器的子字线，其中子字线驱动电压 外汇关闭，浮动。

公开(公告)号：US07177226B2

公开(公告)日：2007-02-13

申请号：US11126677

申请日：2005-05-11

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C8/14

Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.

Abstract translation: 这里公开了通过使用具有两个晶体管的子字线驱动器防止子字线浮动的字线驱动电路。 多个子字线驱动器连接到一个主字线。 多个子字线中的每一个包括PMOS晶体管和串联连接在子字线驱动电压FX与接地电压之间的NMOS晶体管。 浮动防止单元使用具有阈值电压电平的驱动信号来选择主字线为阈值电平的电平，从而防止子字线驱动器的子字线，其中子字线驱动电压 外汇关闭，浮动。

公开(公告)号：US20060221717A1

公开(公告)日：2006-10-05

申请号：US11176345

申请日：2005-07-08

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: G11C7/10

CPC classification number: G11C7/1069 ,  G11C7/1051

Abstract: A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and amplified data onto the GIO line, a GIO termination unit driven responsive to a termination signal for rising or falling a voltage level on the GIO line by a preset level, prior to driving the data onto the GIO line by the read driver, and a receiver driven responsive to the read data transmitted through the GIO line for inverting and amplifying the read data to provide inverted and amplified data. This data output apparatus can enable a high rate data transmission by decreasing a swing width of data transmitted via the GIO line and also reduce a coupling noise on adjacent lines.

Abstract translation: 全局输入和输出（GIO）线中的数据输出装置和方法经由GIO线传送数据。 该数据输出装置包括读取驱动器，该读取驱动器响应于用于反相和放大数据的读取数据的输入，以将反相和放大的数据输出到GIO线上;响应终止信号驱动的GIO终端单元，用于上升或下降电压电平 在读取驱动器将数据驱动到GIO线之前，将GIO线上的GIO线和响应于通过GIO线传输的读取数据驱动的接收器进行反相和放大，以提供反相和放大数据 。 该数据输出装置可以通过减小通过GIO线传输的数据的摆幅来实现高速率数据传输，并且还减少相邻线路上的耦合噪声。

公开(公告)号：US06639854B2

公开(公告)日：2003-10-28

申请号：US10020168

申请日：2001-12-18

Applicant: Young Do Hur ,  Jong Chern Lee

Inventor： Young Do Hur ,  Jong Chern Lee

IPC: G11C700

CPC classification number: G11C29/70 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/1802

Abstract: A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the normal memory cell adjacent to the redundancy memory cell array unit immediately after a word line move time ‘tcycle’ is elasped by using address data.

Abstract translation: 具有冗余电路的半导体存储器件包括正常存储单元阵列单元，用于恢复正常存储单元阵列单元的有缺陷单元的冗余存储单元阵列单元，以及用于操作与冗余相邻的通常存储单元的存储器驱动单元 在字线移动之后立即存储单元阵列单元通过使用地址数据来“tcycle”。

公开(公告)号：US08760181B2

公开(公告)日：2014-06-24

申请号：US12914424

申请日：2010-10-28

Applicant: Sang-Jin Byeon ,  Jong-Chern Lee

Inventor： Sang-Jin Byeon ,  Jong-Chern Lee

IPC: G01R31/36 ,  G11C5/02

CPC classification number: G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract translation: 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US08482331B2

公开(公告)日：2013-07-09

申请号：US12832549

申请日：2010-07-08

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03K5/135 ,  H03K2005/00104

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract translation: 开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值 延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟 响应代码值。

公开(公告)号：US08451037B2

公开(公告)日：2013-05-28

申请号：US13048185

申请日：2011-03-15

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

Abstract translation: 占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比 信号并输出​​检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

公开(公告)号：US08339894B2

公开(公告)日：2012-12-25

申请号：US12970792

申请日：2010-12-16

Applicant: Jae Bum Ko ,  Jong Chern Lee

Inventor： Jae Bum Ko ,  Jong Chern Lee

IPC: G11C8/06

CPC classification number: G11C8/18 ,  G11C8/04

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.

Abstract translation: 半导体存储装置的地址延迟电路包括：控制脉冲生成单元，被配置为在输入读取写入脉冲之后产生与时钟的预定倍数相对应的时间的控制脉冲; 以及延迟单元，被配置为当输入所述控制脉冲时输出内部地址，其中所述内部地址被输入为外部地址。

公开(公告)号：US08314476B2

公开(公告)日：2012-11-20

申请号：US12833672

申请日：2010-07-09

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US20120154002A1

公开(公告)日：2012-06-21

申请号：US13400967

申请日：2012-02-21

Applicant: Seung-Joon AHN ,  Jong-Chern Lee

Inventor： Seung-Joon AHN ,  Jong-Chern Lee

IPC: H03L7/08

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract translation: 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。