公开(公告)号：US08687439B2

公开(公告)日：2014-04-01

申请号：US13181956

申请日：2011-07-13

申请人： Jae Bum Ko ,  Jong Chern Lee

发明人： Jae Bum Ko ,  Jong Chern Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1063 ,  G11C5/14 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/12

摘要： A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.

摘要翻译： 一种半导体存储装置，其具备：具有规定容量和结构的一个以上的半导体芯片; 以及信号电平控制单元，被配置为控制输入到所述一个或多个半导体芯片的外部信号的电平，以便实现使用所述一个或多个半导体芯片的各种容量和结构。

公开(公告)号：US20120249229A1

公开(公告)日：2012-10-04

申请号：US13236970

申请日：2011-09-20

申请人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

发明人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC分类号： H01L25/00

CPC分类号： G11C8/12

摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

摘要翻译： 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US08279702B2

公开(公告)日：2012-10-02

申请号：US12840966

申请日：2010-07-21

申请人： Jae Bum Ko ,  Sang Jin Byeon

发明人： Jae Bum Ko ,  Sang Jin Byeon

IPC分类号： G11C8/00

CPC分类号： H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

摘要翻译： 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

公开(公告)号：US20120124408A1

公开(公告)日：2012-05-17

申请号：US13166094

申请日：2011-06-22

申请人： Sang Jin BYEON ,  Jae Bum Ko

发明人： Sang Jin BYEON ,  Jae Bum Ko

IPC分类号： G06F1/06 ,  H01L23/498

CPC分类号： G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

摘要： A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

摘要翻译： 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

公开(公告)号：US20110267137A1

公开(公告)日：2011-11-03

申请号：US12840966

申请日：2010-07-21

申请人： Jae Bum KO ,  Sang Jin BYEON

发明人： Jae Bum KO ,  Sang Jin BYEON

IPC分类号： H03K19/003

CPC分类号： H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

摘要翻译： 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

公开(公告)号：US20110246104A1

公开(公告)日：2011-10-06

申请号：US12839356

申请日：2010-07-19

申请人： Jae Bum KO ,  Jun Gi CHOI

发明人： Jae Bum KO ,  Jun Gi CHOI

IPC分类号： G06F19/00

CPC分类号： G11C8/12 ,  G11C29/785 ,  G11C29/883 ,  H01L2225/06527

摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

摘要翻译： 一种半导体装置，包括单独的芯片指定代码设置块，其被配置为生成不同值的多个独立芯片指定代码; 单个芯片激活块，其被配置为当各个芯片指定代码与单独的芯片控制代码匹配时，使多个独立芯片激活信号中的各个芯片激活信号对应于各个芯片指定代码; 以及控制块，被配置为响应于芯片选择熔丝信号和测试熔丝信号，将单独的芯片控制代码或输出芯片选择地址设置为单独的芯片控制代码。

公开(公告)号：US20090219775A1

公开(公告)日：2009-09-03

申请号：US12154870

申请日：2008-05-28

申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/12 ,  G11C11/401

摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

公开(公告)号：US07078949B2

公开(公告)日：2006-07-18

申请号：US10750243

申请日：2003-12-31

申请人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

发明人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

IPC分类号： H03L7/06

CPC分类号： H03K5/1565 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814

摘要： An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.

摘要翻译： 模拟延迟锁定环路装置包括用于接收内部时钟信号的第一块和参考时钟信号，以产生正常的多相时钟信号对和虚拟多相时钟信号对; 以及第二块，用于接收参考时钟信号以产生具有基于正常多相时钟信号对和伪多相时钟信号对的校正占空比的延迟锁定内部时钟信号。

公开(公告)号：US06937535B2

公开(公告)日：2005-08-30

申请号：US10696144

申请日：2003-10-28

申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C11/4097

摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

摘要翻译： 存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于 从原始单元块或另一个单元块输出下一个指令。

公开(公告)号：US06930951B2

公开(公告)日：2005-08-16

申请号：US10744322

申请日：2003-12-22

申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

IPC分类号： G11C8/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12

CPC分类号： G11C7/1018

摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.

摘要翻译： 提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。 半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。 驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。