公开(公告)号：US07548469B2

公开(公告)日：2009-06-16

申请号：US11640857

申请日：2006-12-19

Applicant: Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

Inventor： Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

IPC: G11C7/00

CPC classification number: G11C5/145

Abstract: A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

Abstract translation: 电路在半导体存储器件中产生升压电压，其中半导体存储器件包括具有多个非边缘子阵列和至少一个边缘子阵列的存储单元阵列。 电路包括多个升压电压发生器，其被配置为产生具有不同电流驱动能力的升压电压，以激活非边缘子阵列和边缘子阵列，并将升压电压提供给存储单元阵列。

公开(公告)号：US20090136461A1

公开(公告)日：2009-05-28

申请号：US12284117

申请日：2008-09-18

Applicant: Moon Suk Kim ,  Hyun Hee Ahn ,  Jung Hwa Lee ,  Hee Jung Jung ,  Hai Bang Lee ,  Kyung Sook Kim ,  Ju Young Lee

Inventor： Moon Suk Kim ,  Hyun Hee Ahn ,  Jung Hwa Lee ,  Hee Jung Jung ,  Hai Bang Lee ,  Kyung Sook Kim ,  Ju Young Lee

IPC: A61K35/30 ,  C12N5/08 ,  A61P25/00

CPC classification number: C12N5/0618 ,  C12N2501/065 ,  C12N2506/1353 ,  C12N2506/1384

Abstract: The present invention relates to a neuronal differentiation method of adult stem cells using small molecules, more particularly to a method for inducing differentiation of adult stem cells into nerve cells using small molecules, which enables effective differentiation into nerve cells and, thus, is useful in treating intractable CNS disorders such as Parkinson's disease, dementia, Alzheimer's disease and spinal cord injury.

Abstract translation: 本发明涉及使用小分子的成体干细胞的神经元分化方法，更具体地涉及使用小分子诱导成体干细胞分化为神经细胞的方法，其能够有效分化成神经细胞，因此可用于 治疗顽固性CNS疾病如帕金森病，痴呆，阿尔茨海默病和脊髓损伤。

公开(公告)号：US20090111232A1

公开(公告)日：2009-04-30

申请号：US12343035

申请日：2008-12-23

Applicant: Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

Inventor： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

IPC: H01L21/762

CPC classification number: H01L29/945 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/78

Abstract: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

Abstract translation: 提供具有去耦电容器的半导体器件及其制造方法。 半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。 至少一个通道沟槽设置在半导体衬底的单元区域中。 至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。 栅电极设置在半导体衬底的单元区域中并填充沟槽。 第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。 第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。 栅极电介质层介于通道沟槽和栅电极之间。 在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。 在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

公开(公告)号：US07511562B2

公开(公告)日：2009-03-31

申请号：US11865861

申请日：2007-10-02

Applicant: Jeong-hoon Kook ,  Jung-hwa Lee ,  Jung-suk Kim ,  Dae-hwan Kim

Inventor： Jeong-hoon Kook ,  Jung-hwa Lee ,  Jung-suk Kim ,  Dae-hwan Kim

IPC: G05F1/10

CPC classification number: G11C5/145 ,  G11C11/4074 ,  H02M3/07

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract translation: 公开了一种高压发生电路。 在高电压产生电路中，升压节点由多个泵电路预充电并升压，然后放电到输出端子。 在升压节点处的电压明显小于电源电压的情况下，升压节点处的电压升高到电源电压。 在升压节点处的电压明显大于电源电压的情况下，防止在升压节点和电源电压之间形成电流路径，以保持升压节点处的电压明显。

公开(公告)号：US20090065837A1

公开(公告)日：2009-03-12

申请号：US12264490

申请日：2008-11-04

Applicant: Jung-Hwa LEE ,  Si-Woo LEE

Inventor： Jung-Hwa LEE ,  Si-Woo LEE

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/40

Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Abstract translation: 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。

公开(公告)号：US07485911B2

公开(公告)日：2009-02-03

申请号：US11449959

申请日：2006-06-09

Applicant: Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

Inventor： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L29/945 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/78

Abstract: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

Abstract translation: 提供具有去耦电容器的半导体器件及其制造方法。 半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。 至少一个通道沟槽设置在半导体衬底的单元区域中。 至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。 栅电极设置在半导体衬底的单元区域中并填充沟槽。 第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。 第二上电极设置在半导体衬底的第二外围电路区域中，并填充至少第二电容器沟槽。 栅极电介质层介于通道沟槽和栅电极之间。 在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。 在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

公开(公告)号：US07403443B2

公开(公告)日：2008-07-22

申请号：US11452231

申请日：2006-06-14

Applicant: Jung-hwa Lee ,  Hong-jun Lee

Inventor： Jung-hwa Lee ,  Hong-jun Lee

IPC: G11C8/00

CPC classification number: G11C5/025 ,  G11C7/08 ,  G11C2207/065 ,  H01L27/0203 ,  H01L27/105

Abstract: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.

Abstract translation: 公开了一种半导体存储器件，其具有包括交替多个存储单元阵列和交替多个读出放大器块和连接块之间布置的字线驱动块的布局，使得每个读出放大器块位于对应的存储单元阵列 ，并且每个连接块位于对应的字线驱动块的横向。 每个读出放大器块交替地包括电源电压驱动器和地电压驱动器之一。

公开(公告)号：US20080024201A1

公开(公告)日：2008-01-31

申请号：US11865861

申请日：2007-10-02

Applicant: Jeong-hoon KOOK ,  Jung-hwa LEE ,  Jung-suk KIM ,  Dae-hwan KIM

Inventor： Jeong-hoon KOOK ,  Jung-hwa LEE ,  Jung-suk KIM ,  Dae-hwan KIM

IPC: G05F3/02

CPC classification number: G11C5/145 ,  G11C11/4074 ,  H02M3/07

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

公开(公告)号：US07295058B2

公开(公告)日：2007-11-13

申请号：US11103647

申请日：2005-04-12

Applicant: Jeong-hoon Kook ,  Jung-hwa Lee ,  Jung-suk Kim ,  Dae-hwan Kim

Inventor： Jeong-hoon Kook ,  Jung-hwa Lee ,  Jung-suk Kim ,  Dae-hwan Kim

IPC: G05F1/10

CPC classification number: G11C5/145 ,  G11C11/4074 ,  H02M3/07

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract translation: 公开了一种高压发生电路。 在高电压产生电路中，升压节点由多个泵电路预充电并升压，然后放电到输出端子。 在升压节点处的电压明显小于电源电压的情况下，升压节点处的电压升高到电源电压。 在升压节点处的电压明显大于电源电压的情况下，防止在升压节点和电源电压之间形成电流路径，以保持升压节点处的电压明显。

公开(公告)号：US20070057981A1

公开(公告)日：2007-03-15

申请号：US11496579

申请日：2006-08-01

Applicant: Jung-hwa Lee ,  Jung-hwan Kim

Inventor： Jung-hwa Lee ,  Jung-hwan Kim

IPC: B41J2/195

CPC classification number: B41J2/16526 ,  B41J2/155 ,  B41J2/16585 ,  B41J2002/1657

Abstract: A method and apparatus to perform a spitting service on a wide array print head includes detecting dot counts of print heads after a predetermined page is printed, determining spitting service levels corresponding to the detected dot counts, and executing spitting services for the print heads according to the spitting service levels. Accordingly, spitting services of a plurality of print heads of the wide array print head can be classified into several levels for execution, so that the print heads can maintain an optimum condition and provide a best printing quality, and unnecessary ink consumption can be reduced.

Abstract translation: 在宽阵列打印头上执行吐痰服务的方法和装置包括：在打印预定页面之后检测打印头的点数，确定与检测到的点计数相对应的吐痰服务等级，以及根据打印头执行吐痰服务 吐痰服务水平。 因此，宽阵列打印头的多个打印头的吐痰服务可以分为几个级别执行，使得打印头可以保持最佳状态并提供最佳的打印质量，并且可以减少不必要的墨水消耗。