公开(公告)号：US08751975B2

公开(公告)日：2014-06-10

申请号：US13479076

申请日：2012-05-23

Applicant: Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.

Abstract translation: 一种方法包括确定用于形成集成电路的模型参数，以及使用模型参数生成技术文件。 该技术文件包括C_worst表，C_best表和C_nominal表中的至少两个。 当包括布局图案的光刻掩模相对于彼此移动时，C_worst表存储集成电路的布局图案之间的最大寄生电容。 当光刻掩模相对于彼此移动时，C_best表存储布局图案之间的最小寄生电容。 当光刻掩模不相对于彼此移动时，C_nominal表存储布局图案之间的标称寄生电容。 该技术文件体现在有形的非暂时性存储介质上。

公开(公告)号：US08694938B2

公开(公告)日：2014-04-08

申请号：US13534526

申请日：2012-06-27

Applicant: Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

Inventor： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract translation: 除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。 也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。 由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。 例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。 可以使用一组RC值将离散器件建模为宏器件。 以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

公开(公告)号：US20140007028A1

公开(公告)日：2014-01-02

申请号：US13534526

申请日：2012-06-27

Applicant: Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

Inventor： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract translation: 除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。 也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。 由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。 例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。 可以使用一组RC值将离散器件建模为宏器件。 以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

公开(公告)号：US20130246986A1

公开(公告)日：2013-09-19

申请号：US13535709

申请日：2012-06-28

Applicant: Chin-Cheng KUO ,  Wei-Yi HU ,  Jui-Feng KUAN ,  Yi-Kan CHENG

Inventor： Chin-Cheng KUO ,  Wei-Yi HU ,  Jui-Feng KUAN ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

Abstract translation: 一种方法包括（a）产生一组样本，每个样本表示相应的一组半导体制造工艺变化值; （b）基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; （c）在不执行蒙特卡罗模拟的情况下，基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及（d）如果估计的收益率测量低于规格收益率值，则输出设计修改适当的指示。

公开(公告)号：US20130191796A1

公开(公告)日：2013-07-25

申请号：US13354707

申请日：2012-01-20

Applicant: Wen-Hao CHEN ,  Yuan-Te HOU ,  Yi-Kan CHENG

Inventor： Wen-Hao CHEN ,  Yuan-Te HOU ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5077

Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

Abstract translation: 公开了改进利用多重图案化技术（MPT）的集成电路（IC）设计的方法。 所述方法包括配置集成电路的第一布局，其具有至少一层具有通过至少两个掩模的制造而形成的特征的层。 该至少一层包括多个活动单元和多个备用单元。 第二布局被配置为重新路由备用单元和活动单元，其中重新路由使用多个备用单元的至少一部分。 比所有至少两个掩模更少，以配置第二个布局。

公开(公告)号：US08473873B2

公开(公告)日：2013-06-25

申请号：US13224486

申请日：2011-09-02

Applicant: Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

Abstract translation: 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

公开(公告)号：US08418117B2

公开(公告)日：2013-04-09

申请号：US12831982

申请日：2010-07-07

Applicant: Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207

Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

Abstract translation: 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。

公开(公告)号：US20130061186A1

公开(公告)日：2013-03-07

申请号：US13224486

申请日：2011-09-02

Applicant: Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

公开(公告)号：US20130014070A1

公开(公告)日：2013-01-10

申请号：US13176823

申请日：2011-07-06

Applicant: Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

Inventor： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

Abstract translation: 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

公开(公告)号：US08286119B2

公开(公告)日：2012-10-09

申请号：US12617046

申请日：2009-11-12

Applicant: Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

Inventor： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract translation: 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。